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| ? 2013 microchip technology inc. ds22331a-page 1 synchronous buck features: ? input voltage: 4.5v to 32v ? output voltage: 0.5v to 3.6v ? switching frequency: 100 khz to 1.6 mhz ? quiescent current: 5 ma typical ? high-drive: - +5v gate drive - 1a/2a source current - 1a/2a sink current ? low-drive: - +5v gate drive - 2a source current - 4a sink current ? peak current mode control ? differential remote output sense ? multi-phase systems: - master or slave - frequency synchronized - common error signal ? multiple output systems: - master or slave - frequency synchronized ? configureable parameters: - overcurrent limit - input under voltage lockout - output overvoltage - output under voltage - internal analog compensation - soft start profile - synchronous driver dead time - switching frequency ? thermal shutdown microcontroller features: ? precision 8 mhz internal oscillator block: - factory calibrated ? interrupt capable -firmware - interrupt-on-change pins ? only 35 instructions to learn ? 4096 words on-chip program memory ? high endurance flash: - 100,000 write flash endurance - flash retention: >40 years ? watchdog timer (wdt) with independent oscillator for reliable operation ? programmable code protection ? in-circuit debug (icd) via two pins ? in-circuit serial programming? (icsp?) via two pins ? 14 i/o pins and one input-only pin - 3 open drain pins ? analog-to-digital converter (adc): - 10-bit resolution - 12 internal channels - 8 external channels ? timer0: 8-bit timer/counter with 8-bit prescaler ? enhanced timer1: - 16-bit timer/counter with prescaler - 2 selectable clock sources ? timer2: 8-bit timer/counter with prescaler - 8-bit period register ? i 2 c tm communication: - 7-bit address masking - 2 dedicated address registers - smbus/pmbus tm compatibility mcp19111 digitally enhanced power analog controller with integrated synchronous driver
mcp19111 ds22331a-page 2 ? 2013 microchip technology inc. pin diagram ? 28-pin qfn (mcp19111) mcp19111 gpa2 gpb4 gpa4 gpb7 gpb0 gpa1 gpa0 gpa3 gpa7 v in gpb2 gpa5/mclr p gnd ldrv v dr phase hdrv boot v dd gpb1 -v sen +v sen +i sen -i sen gpa6 gnd gpb6 gpb5 1 2 3 4 5 6 715 8 9 10 11 12 13 14 16 17 18 19 20 21 26 25 24 23 22 28 27 exp-29 ? 2013 microchip technology inc. ds22331a-page 3 mcp19111 table 1: 28-pin summary i/o 28-pin qfn ansel a/d timers mssp interrupt pull-up basic additional gpa0 1 y an0 ? ? ioc y ? analog debug output ( 1 ) gpa1 2 y an1 ? ? ioc y ? sync signal in/out ( 2 , 3 ) gpa2 3 y an2 t0cki ? ioc int y ? ? gpa3 5 y an3 ? ioc y ? ? gpa4 9 n ? ? ? ioc n ? ? gpa5 8 n ? ? ? ioc ( 4 ) y ( 5 ) mclr ? gpa6 7 n ? ? ? ioc n ? gpa7 6 n ? ? scl ioc n ? gpb0 10 n ? ? sda ioc n ? ? gpb1 26 y an4 ? ? ioc y ? error signal in/out ( 3 ) gpb2 28 y an5 ? ? ioc y ? ? gpb4 4 y an6 ? ? ioc y icspdat icddat ? gpb5 27 y an7 ? ? ioc y icspclk icdclk alternate sync signal in/out ( 2 , 3 ) gpb6 21 n ? ? ? ioc y ? ? gpb7 11 n ? ? ? ioc y ? ? v in 13 n ? ? ? ? ? v in device input voltage v dr 16 n ? ? ? ? ? v dr gate drive supply input voltage v dd 20 n ? ? ? ? ? v dd internal regulator output gnd 12 n ? ? ? ? ? gnd small signal ground p gnd 14 n ? ? ? ? ? ? large signal ground ldrv 15 n ? ? ? ? ? ? low-side mosfet connection hdrv 18 n ? ? ? ? ? ? high-side mosfet connection phase 17 n ? ? ? ? ? ? switch node boot 19 n ? ? ? ? ? ? floating bootstrap supply +v sen 24 n ? ? ? ? ? ? output voltage differential sense -v sen 25 n ? ? ? ? ? ? output voltage differential sense +i sen 23 n ? ? ? ? ? ? current sense input -i sen 22 n ? ? ? ? ? ? current sense input note 1: the analog debug output is selected when the atstcon mcp19111 ds22331a-page 4 ? 2013 microchip technology inc. table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 pin description ............................................................................................................. .............................................................. 10 3.0 functional description ...................................................................................................... .......................................................... 15 4.0 electrical characteristics .................................................................................................. .......................................................... 21 5.0 digital electrical characteristics .......................................................................................... ....................................................... 27 6.0 configuring the mcp19111.................................................................................................... ..................................................... 35 7.0 typical performance curves .................................................................................................. .................................................... 51 8.0 system bench testing ........................................................................................................ ........................................................ 55 9.0 device calibration .......................................................................................................... ............................................................ 57 10.0 relative efficiency measurement ............................................................................................ ................................................... 65 11.0 memory organization ........................................................................................................ ......................................................... 67 12.0 device configuration ....................................................................................................... ........................................................... 79 13.0 oscillator modes........................................................................................................... .............................................................. 81 14.0 resets ..................................................................................................................... ................................................................... 83 15.0 interrupts ................................................................................................................. ................................................................... 91 16.0 power-down mode (sleep) .................................................................................................... .................................................... 99 17.0 watchdog timer (wdt)....................................................................................................... ..................................................... 101 18.0 flash program memory control ............................................................................................... ................................................ 103 19.0 i/o ports .................................................................................................................. ................................................................. 109 20.0 interrupt-on-change ........................................................................................................ .........................................................119 21.0 internal temperature indicator module...................................................................................... ............................................... 121 22.0 analog-to-digital converter (adc) module ................................................................................... ........................................... 123 23.0 timer0 module.............................................................................................................. ............................................................ 133 24.0 timer1 module with gate control............................................................................................ ................................................. 135 25.0 timer2 module.............................................................................................................. ............................................................ 138 26.0 pwm module................................................................................................................. ........................................................... 141 27.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 145 28.0 in-circuit serial programming? (icsp?) ..................................................................................... .......................................... 189 29.0 instruction set summary .................................................................................................... ...................................................... 191 30.0 development support........................................................................................................ ....................................................... 201 31.0 packaging information...................................................................................................... ........................................................ 205 appendix a: revision history................................................................................................... .......................................................... 209 index .......................................................................................................................... .........................................................................211 the microchip web site ......................................................................................................... ............................................................ 217 customer change notification service ........................................................................................... ................................................... 217 customer support ............................................................................................................... ............................................................... 217 reader response ................................................................................................................ .............................................................. 218 product identification system.................................................................................................. ........................................................... 219 ? 2013 microchip technology inc. ds22331a-page 5 mcp19111 to our valued customers it is our intention to provide our valued customers with the best documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regar ding this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our world wide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s world wide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. mcp19111 ds22331a-page 6 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 7 mcp19111 1.0 device overview the mcp19111 is a highly integrated, mixed signal, analog pulse-width modulation (pwm) current mode controller with an integrated microcontroller core for synchronous dc/dc step-down applications. since the mcp19111 uses traditional analog control circuitry to regulate the output of the dc/dc converter, the integra- tion of the pic ? microcontroller mid-range core is used to provide complete customization of device operating parameters, start-up and shut down profiles, protection levels and fault handling procedures. the mcp19111 is designed to efficiently operate from a single 4.5v to 32v supply. it features integrated synchronous drivers, bootstrap device, internal linear regulator and 4 kw nonvolatile memory all in a space-saving 28-pin 5 mm x 5mm qfn package. after initial device configuration using microchip?s mplab ? x integrated development environment (ide) software, the pmbus or i 2 c can be used by a host to communicate with, or modify, the operation of the mcp19111. two internal linear regulators generate two 5v rails. one 5v rail is used to provide power for the internal analog circuitry and is contained on-chip. the second 5v rail provides power to the pic device and is present on the v dd pin. it is recommended that a 1 f capacitor be placed between v dd and p gnd . the v dd pin may also be directly connected to the v dr pin, or connected through a low-pass rc filter. the v dr pin provides power to the internal synchronous driver. figure 1-1: typical application circuit hdrv boot phase ldrv v in v dd v dr +i sen -i sen +v sen -v sen gnd p gnd gpb0 gpa7 gpa4 gpa1 gpb6 gpb7 gpa3 gpb2 gpa2 gpa5 gpb4 gpb5 gpa0 gpb1 gpa6 mclr icdclk icddat sda scl smbus alert sync addr0 addr1 cntl pgood track mcp19111 v in +v out -v out x i cd programmer mplab ? mcp19111 ds22331a-page 8 ? 2013 microchip technology inc. figure 1-2: mcp19111 sy nchronous buck block diagram phase hdrv ldrv v in v dd boot v in v out vdac av dd ldo1 ldo2 bias gen bgap uvlo 4 4 v zc 5 slave mode master mode vregref uv ref ov ref 8+5 8 8 v out v out v out ov uv bgap lo_on 4 av dd v dd 5 oc comp v in dly 4 lvl_sft pic core debug mux lo_on ov uv v in_ok oc flag a/d mux v dr -i sen +v sen -v sen +i sen +i sen -i sen +v sen -v sen gnd pgnd i/o(digital signals) 15 i/o i/o 6 r 5r v dr dly 4 4 3 to adc csdgen bit dc current sense gain ac current sense gain ? 2013 microchip technology inc. ds22331a-page 9 mcp19111 figure 1-3: microcontro ller core block diagram flash program memory 13 data bus 8 14 program bus instruction reg program counter ram file registers direct addr 7 ram addr 9 addr mux indirect addr fsr reg status reg mux alu w reg instruction decode & control timing generation testclkin porta 8 8 8 3 8 level stack 256 4k x 14 bytes (13-bit) power-up timer power-on reset watchdog timer mclr v in v ss timer0 timer1 t0cki configuration 8 mhz internal oscillator timer2 mssp gpa0 gpa1 gpa2 gpa3 gpa4 gpa5 analog interface sda scl pmdatl eeaddr self read/ write flash memory registers portb gpb0 gpb1 gpb2 gpb6 gpb4 pwm gpb5 gpa6 gpa7 gpb7 mcp19111 ds22331a-page 10 ? 2013 microchip technology inc. 2.0 pin description the 28-lead mcp19111 device features pins that have multiple functions associated with each pin. table 2-1 provides a description of the different functions. see section 2.1 ?detailed pin functional description? for more detailed information. table 2-1: mcp19111 pinout description name function input type output type description gpa0/an0/analog_test gpa0 ttl cmos general purpose i/o an0 an ? a/d channel 0 input. analog_test ? ? internal analog signal multiplexer output ( 1 ) gpa1/an1/clkpin gpa1 ttl cmos general purpose i/o an1 an ? a/d channel 1 input. clkpin ? ? switching frequency clock input or output ( 2 , 3 ) gpa2/an2/t0cki/int gpa2 ttl cmos general purpose i/o an2 an ? a/d channel 2 input t0cki st ? timer0 clock input int st ? external interrupt gpa3/an3 gpa3 ttl cmos general purpose i/o an3 an ? a/d channel 3 input gpa4 gpa4 ttl od general purpose i/o gpa5/mclr gpa5 ttl ? general purpose input only mclr st ? master clear with internal pull-up gpa6 gpa6 st cmos general purpose i/o gpa7/scl gpa7 st od general purpose open drain i/o scl i 2 codi 2 c clock gpb0/sda gpb0 ttl od sda i 2 codi 2 c data input/output gpb1/an4/eapin gpb1 ttl cmos general purpose i/o an4 an ? a/d channel 4 input eapin ? ? error amplifier signal input/output ( 3 ) gpb2/an5 gpb2 ttl cmos general purpose i/o an5 an ? a/d channel 5 input gpb4/an6/icspdat gpb4 ttl cmos general purpose i/o an6 an ? a/d channel 6 input icspdat st cmos primary serial programming data i/o legend: an = analog input or output cmos =cmos compatible input or output od = open drain ttl = ttl compatible input st =schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c note 1: analog test is selected when the atstcon ? 2013 microchip technology inc. ds22331a-page 11 mcp19111 gpb5/an7/icspclk/ alt_clkpin gpb5 ttl cmos general purpose i/o an7 an ? a/d channel 7 input iscpclk st ? primary serial programming clock alt_clkpin ? ? alternate switching frequency clock input or output ( 2 , 3 ) gpb6 gpb6 ttl cmos general purpose i/o gpb7 gpb7 ttl cmos general purpose i/o v in v in ? ? device input supply voltage v dd v dd ? ? internal +5v ldo output pin v dr v dr ? ? gate drive supply input voltage pin gnd gnd ? ? small signal quiet ground p gnd p gnd ? ? large signal power ground ldrv ldrv ? ? high-current drive signal connected to the gate of the low-side mosfet hdrv hdrv ? ? floating high-current drive signal connected to the gate of the high-side mosfet phase phase ? ? synchronous buck switch node connection boot boot ? ? floating bootstrap supply +v sen +v sen ? ? positive input of the output voltage sense differential amplifier -v sen -v sen ? ? negative input of the output voltage sense differential amplifier +i sen +i sen ? ? current sense input -i sen -i sen ? ? current sense input ep ? ? ? exposed thermal pad table 2-1: mcp19111 pinout description (continued) name function input type output type description legend: an = analog input or output cmos =cmos compatible input or output od = open drain ttl = ttl compatible input st =schmitt trigger input with cmos levels i 2 c = schmitt trigger input with i 2 c note 1: analog test is selected when the atstcon mcp19111 ds22331a-page 12 ? 2013 microchip technology inc. 2.1 detailed pin functional description 2.1.1 gpa0 pin gpa0 is a general purpose ttl input or cmos output pin whose data direction is controlled in TRISGPA. an internal weak pull-up and interrupt-on-change are also available. an0 is an input to the a/d. to configure this pin to be read by the a/d on channel 0, bits trisa0 and ansa0 must be set. when the atstcon ? 2013 microchip technology inc. ds22331a-page 13 mcp19111 2.1.10 gpb1 pin gpb1 is a general purpose ttl input or cmos output pin whose data direction is controlled in trisgpb. an internal weak pull-up and interrupt-on-change are also available. an4 is an input to the a/d. to configure this pin to be read by the a/d on channel 4, bits trisb1 and ansb1 must be set. when the mcp19111 is configured as a multiple output or multi-phase master or slave, this pin is config- ured to be the error amplifier signal input or output. see section 3.10.6 ?multi-phase system? and section 3.10.7 ?multiple output system? , for more information. 2.1.11 gpb2 pin gpb2 is a general purpose ttl input or cmos output pin whose data direction is controlled in trisgpb. an internal weak pull-up and interrupt-on-change are also available. an5 is an input to the a/d. to configure this pin to be read by the a/d on channel 5, bits trisb2 and ansb2 must be set. 2.1.12 gpb4 pin gpb4 is a general purpose ttl input or cmos output pin whose data direction is controlled in trisgpb. an internal weak pull-up and interrupt-on-change are also available. an6 is an input to the a/d. to configure this pin to be read by the a/d on channel 6, bits trisb4 and ansb4 must be set. iscpdat is the primary serial programming data input function. this is used in conjunction with icspclk to serial program the device. 2.1.13 gbp5 pin gpb5 is a general purpose ttl input or cmos output pin whose data direction is controlled in trisgpb. an internal weak pull-up and interrupt-on-change are also available. an7 is an input to the a/d. to configure this pin to be read by the a/d on channel 7, bits trisb5 and ansb5 must be set. iscpclk is the primary serial programming clock func- tion. this is used in conjunction with icspdat to serial program the device. this pin can also be configured as an alternate switch- ing frequency synchronization input or output, alt_clkpin, for use in multiple output or multi-phase systems. see section 19.1 ?alternate pin function? for more information. 2.1.14 gpb6 pin gpb6 is a general purpose ttl input or cmos output pin whose data direction is controlled in trisgpb. an internal weak pull-up and interrupt-on-change are also available. 2.1.15 gpb7 pin gpb7 is a general purpose ttl input or cmos output pin whose data direction is controlled in trisgpb. an internal weak pull-up and interrupt-on-change are also available. 2.1.16 v in pin device input power connection pin. it is recommended that capacitance be placed between this pin and the gnd pin of the device. 2.1.17 v dd pin the output of the internal +5.0v regulator is connected to this pin. it is recommended that a 1.0 f bypass capacitor be connected between this pin and the gnd pin of the device. the bypass capacitor should be placed physically close to the device. 2.1.18 v dr pin the 5v supply for the low-side driver is connected to this pin. the pin can be connected by an rc filter to the v dd pin. 2.1.19 gnd pin gnd is the small signal ground connection pin. this pin should be connected to the exposed pad, on the bottom of the package. 2.1.20 p gnd pin connect all large signal level ground returns to p gnd . these large-signal level ground traces should have a small loop area and minimal length to prevent coupling of switching noise to sensitive traces. 2.1.21 ldrv pin the gate of the low-side or rectifying mosfet is connected to ldrv. the pcb tracing connecting ldrv to the gate must be of minimal length and appropriate width to handle the high peak drive currents and fast voltage transitions. 2.1.22 hdrv pin the gate of the high-side mosfet is connected to hdrv. this is a floating driver referenced to phase. the pcb trace connecting hdrv to the gate must be of minimal length and appropriate width to handle the high peak drive current and fast voltage transitions. mcp19111 ds22331a-page 14 ? 2013 microchip technology inc. 2.1.23 phase pin the phase pin provides the return path for the high- side gate driver. the source of the high-side mosfet, drain of the low-side mosfet and the inductor are connected to this pin. 2.1.24 boot pin the boot pin is the floating bootstrap supply pin for the high-side gate driver. a capacitor is connected between this pin and the phase pin to provide the necessary charge to turn on the high-side mosfet. 2.1.25 +v sen pin the non-inverting input of the unity gain amplifier used for output voltage remote sensing is connected to the +v sen pin. this pin can be internally pulled-up to v dd by setting pe1 ? 2013 microchip technology inc. ds22331a-page 15 mcp19111 3.0 functional description 3.1 linear regulators two internal linear regulators generate two 5v rails. one 5v rail is used to provide power for the internal analog circuitry and is contained on-chip. the second 5v rail provides power to the internal pic core and it is present on the v dd pin. it is recommended that a 1 f capacitor be placed between v dd and p gnd . the v dr pin provides power to the internal synchronous mosfet driver. v dd can be directly connected to v dr or connected through a low-pass rc filter to provide noise filtering. a 1 f ceramic bypass capacitor should be placed between v dr and p gnd . when connecting v dd to v dr , the gate drive current required to drive the external mosfets must be added to the mcp19111 quiescent current, i q(max) . this total current must be less than the maximum current, i dd-out , available from v dd that is specified in section 4.2 ?electrical characteristics? . equation 3-1: total regulator current equation 3-2: gate drive current alternatively, an external regulator can be used to power the synchronous driver. an external 5v source can be connected to v dr . the amount of current required from this external source can be found in equation 3-2 . care must be taken that the voltage applied to v dr does not exceed the maximum ratings found in section 4.1 ?absolute maximum ratings (?)? . 3.2 internal synchronous driver the internal synchronous driver is capable of driving two n-channel mosfets in a synchronous rectified buck converter topology. the gate of the floating mosfet is connected to the hdrv pin. the source of this mosfet is connected to the phase pin. the hdrv pin source and sink current is configurable. by setting the drvstr bit in the pe1 register, the high- side is capable of sourcing and sinking a peak current of 1a. by clearing this bit, the source and sink peak current is 2a. the mosfet connected to the ldrv pin is not floating. the low-side mosfet gate is connected to the ldrv pin and the source of this mosfet is connected to p gnd . the drive strength of the ldrv pin is not configurable. this pin is capable of sourcing a peak current of 2a. the peak sink current is 4a. this helps keep the low-side mosfet off when the high-side mosfet is turning on. 3.2.1 mosfet driver dead time the mosfet driver dead time is defined as the time between one drive signal going low and the complimentary drive signal going high. refer to figure 6-2 . the mcp19111 has the capability to adjust both the high-side and low-side driver dead time independently. the adjustment of the driver dead time is controlled by the deadcon register and is adjustable in 4 ns increments. 3.2.2 mosfet driver control the mcp19111 has the ability to disable the entire synchronous driver or just one side of the synchronous drive signal. the bits that control the mosfet driver can be found in the register 8-1 . by setting atstcon mcp19111 ds22331a-page 16 ? 2013 microchip technology inc. individual control of the hdrv or ldrv signal is accomplished by setting or clearing the hidis or lodis bits in the atstcon register. when either driver is disabled, the output signal is set low. 3.3 output voltage the output voltage is configured by the settings contained in the ovccon and ovfcon registers. no external resistor divider is needed to set the output voltage. refer to section 6.10 ?output voltage configuration? . the mcp19111 contains a unity gain differential amplifier used for remote sensing of the output voltage. connect the +v sen and -v sen pins directly at the load for better load regulation. the +v sen and -v sen are the positive and negative inputs, respectively, of the differential amplifier. 3.4 switching frequency the switching frequency is configurable over the range of 100 khz to 1.6 mhz. the timer2 module is used to generate the hdrv/ldrv switching frequency. refer to section 26.0 ?pwm module? for more information. example 3-1 shows how to configure the mcp19111 for a switching frequency of 300 khz. example 3-1: co nfiguring f sw 3.5 compensation the mcp19111 is an analog peak current mode controller with integrated adjustable compensation. the cmpzcon register is used to adjust the compensation zero frequency and gain. figure 3-1 shows the internal compensation network with the output differential amplifier. figure 3-1: simplified internal compensation 3.6 slope compensation in current mode control systems, slope compensation needs to be added to the control path to help prevent subharmonic oscillation when operating with greater than 50% duty cycle. in the mcp19111, a negative slope is added to the error amplifier output signal before it is compared to the current sense signal. the amount of slope added is controlled by the slpcrcon register, register 6-7 . the amount of slope compensation added should be equal to the inductor current down slope during the high-side off time. 3.7 current sense the output current is differentially sensed by the mcp19111. the sense element can be either a resistor placed in series with the output, or the series resistance of the inductor. if the inductor series resistance is used, a filter is needed to remove the large ac component of the voltage that appears across the inductor and leave only the small ac voltage that appears across the inductor resistance, as shown in figure 3-2 . this small ac voltage is representative of the output current. figure 3-2: inductor current sense filter banksel t2con clrf t2con ;turn off timer2 clrf tmr2 ;initialize module movlw 0x19 ;fsw=300 khz movwf pr2 movlw 0x0a ;max duty cycle=40% movwf pwmrl movlw 0x00 ;no phase shift movwf pwmphl movlw 0x04 ;turn on timer2 movwf t2con note 1: to enable the slope compensation circuitry, the abecon ? 2013 microchip technology inc. ds22331a-page 17 mcp19111 the value of r s and c s can be found by using equation 3-3 . when the current sense filter time constant is set equal to the inductor time constant, the voltage appearing across c s approximates the current flowing in the inductor, multiplied by the inductor resistance. equation 3-3: calculating filter values both ac gain and dc gain can be added to the current sense signal. refer to section 6.3 ?current sense ac gain? and section 6.4 ?current sense dc gain? for more information. 3.7.1 placement of the current sense filter components the amplitude of the current sense signal is typically less than 100 mv peak-to-peak. therefore, the small signal current sense traces are very susceptible to circuit noise. when designing the printed circuit board, placement of r s and c s is very important. the +i sen and -i sen traces should be routed parallel to each other with minimum spacing. this kelvin sense routing technique helps minimize noise sensitivity. the filter capacitor (c s ), should be placed as close to the mcp19111 as possible. this will help filter any noise that is injected onto the current sense lines. the trace connecting c s to the inductor should occur directly at the inductor and not at any other +v sen trace. the filter resistor (r s ), should be placed close to the inductor. see figure 3-3 for component placement. care should also be taken to avoid routing the +i sen and -i sen traces near the high current switching nodes of the hdrv, ldrv, phase, or boost traces. it is recommended that a ground layer be placed between these high current traces and the small signal current sense traces. figure 3-3: current sense filter component placement l r l ----- - r s c s ? ?? = where: - l is the inductance value of the output inductor -r l is the series resistance of the output inductor -r s is the current sense filter resistor -c s is the current sense filter capacitor +i sen -i sen inductor to load to phase r s c s mcp19111 ds22331a-page 18 ? 2013 microchip technology inc. 3.8 protection features 3.8.1 input under voltage lockout the input under voltage lockout (uvlo) threshold is configurable by the vinlvl register, register 6-1 . when the voltage at the v in pin of the mcp19111 is below the configurable threshold, the pir2 ? 2013 microchip technology inc. ds22331a-page 19 mcp19111 3.8.5 overtemperature the mcp19111 features a hardware overtemperature shutdown protection typically set at +160c. no firmware fault-handling procedure is required to shutdown the mcp19111 for an overtemperature condition. 3.9 pic microcontroller core integrated into the mcp19111 is the pic microcontroller mid-range core. this is a fully functional microcontroller, allowing proprietary features to be implemented. setting the config mcp19111 ds22331a-page 20 ? 2013 microchip technology inc. 3.10.3 output power good the output voltage measured between the +v sen and -v sen pins can be monitored by the internal adc. in firmware, when this adc reading matches a user defined power good value, a gpio can be toggled to indicate the system output voltage is within a specified range. delays, hysteresis and time out values can all be configured in firmware. 3.10.4 output voltage soft-start during start-up, soft start of the output voltage is accomplished in firmware. by using one of the internal timers and incrementing the ovccon or ovfcon register on a timer overflow, very long soft start times can be achieved. 3.10.5 output voltage tracking the mcp19111 can be configured to track another voltage signal at start-up or shutdown. the adc is configured to read a gpio that has the desired tracking voltage applied to it. the firmware then handles the tracking of the internal output voltage reference to this adc reading. 3.10.6 multi-phase system in a multi-phase system the output of each converter is connected together. there is one master device that sets the system switching frequency and provides each slave device with an error signal, in order to regulate the output to the same value. the mcp19111 can be configured as a multi-phase master or slave by the setting of the mltph<2:0> bits in the buffcon register ( register 8-2 ). when set as a multi-phase master device, the internal switching fre- quency clock is connected to gpa1 and the output of the error amplifier is connected to gpb1. the gpios need to be configured as outputs. when set as a multi-phase slave device, the gpa1 pin is configured as the clkpin function. the switching frequency clock from the master device must be connected to gpa1. the slave device will synchronize its internal switching frequency clock to the master clock. phase shift can be applied by setting the pwmphl register of the slave device. the slave gpb1 pin is configured as the error signal input pin (eapin). the master error amplifier output must be connected to gpb1. gain can be added to the master error amplifier output signal by the slvgncon register setting ( register 6-8 ). the slave device will use this master error signal to regulate the output voltage. when set as a slave device, gpa1 and gpb1 need to be configured as inputs. refer to section 26.1 ?standard pulse- width modulation (pwm) mode? for additional information . 3.10.7 multiple output system in a multiple output system, the switching frequency of each converter should be synchronized to a master clock to prevent beat frequencies from developing. phase shift is often added to the master clock to help smooth the system input current. the mcp19111 has the ability to function as a multiple output master or slave by setting the appropriate mltph<2:0> bits in the buffcon register ( register 8-2 ). when configured as a multiple output master, the gpa1 pin is set as the clkpin output function. the internal switching frequency clock is applied to this pin and is to be connected to the gpa1 pin of the slave units. when configured as a multiple output slave, the gpa1 pin is set as the clkpin input function. the switching frequency clock of the master device is connected to this pin. phase shift can be applied by appropriately setting the pwmphl register of the slave device. refer to section 26.1 ?standard pulse-width modulation (pwm) mode? . 3.10.8 system bench testing the mcp19111 is a highly integrated controller. to facilitate system prototyping, various internal signals can be measured by configuring the mcp19111 in bench test mode. to accomplish this, the atstcon ? 2013 microchip technology inc. ds22331a-page 21 mcp19111 4.0 electrical characteristics 4.1 absolute maximum ratings (?) v in ?v gnd ............................................................................................................................... ................... -0.3v to +32v v boot - v in ............................................................................................................................... .................. -0.3v to +6.5v v phase (continuous) ................................................................................................................... ..... gnd ? 0.3v to +30v v phase (transient < 100 ns)............................................................................................................ . gnd ? 5.0v to +30v v dd internally generated .......................................................................................................... .........................+5v 20% v hdrv , hdrv pin..........................................................................................................+v phase ? 0.3v to v boot +0.3v v ldrv , ldrv pin............................................................................................................. +(v gnd ? 0.3v) to (v dd +0.3v) voltage on mclr with respect to gnd.................................................................................................... -0.3v t o+13.5v maximum voltage: any other pin..................................................................................... +(v gnd ? 0.3v) to (v dd +0.3v) maximum output current sunk by any single i/o pin .............................................................................. .................25 ma maximum output current sourced by any single i/o pin ........................................................................... ...............25 ma maximum current sunk by all gpio ............................................................................................... .........................65 ma maximum current sourced by all gpio ............................................................................................ .......................65 ma esd protection on all pins (hbm) ............................................................................................... ............................ 1.0 kv esd protection on all pins (mm) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????????????????? ????????????? ? 100 v ? notice: stresses above those listed under ?maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. mcp19111 ds22331a-page 22 ? 2013 microchip technology inc. 4.2 electrical characteristics electrical specifications: unless otherwise noted, v in = 12v, v ref = 1.2v, f sw =300khz, t a =+25c. boldface specifications apply over the t a range of -40c to +125c. parameter symbol min typ max units conditions input input voltage v in 4.5 ? 32 v input quiescent current i q ?5 10 ma not switching shutdown current i shdn ?1.8 2.2 ma note 4 adjustable input under voltage lockout range uvlo 3 ? 32 v vinlvl is a log dac input under voltage lockout hysteresis uvlo hys ? 13 ? % hysteresis applied to adjustable uvlo setpoint overcurrent overcurrent minimum threshold oc min ?160?mv overcurrent maximum threshold oc max ?620?mv overcurrent mid-scale threshold oc mid 240 400 550 mv overcurrent step size oc step_size 10 15 20 mv adjustable oc leading edge blanking minimum set point leb min ?114?ns adjustable oc leading edge blanking maximum set point leb max ?780?ns current sense current sense minimum ac gain i ac_gain ?0?db current sense maximum ac gain i ac_gain ?22.8?db current sense ac gain mid set point i ac_gain 8.5 11.5 14 db current sense ac gain step size i ac_gain_step ?1.5?db current sense ac gain offset voltage i ac_offset -175 9 135 mv current sense minimum dc gain i dc_gain ?19.5?db current sense maximum dc gain i dc_gain ?35.7?db current sense dc gain mid set point i dc_gain 27 28.6 30.3 db current sense dc gain step size i dc_gain_step ?2.3?db note 1: ensured by design. not production tested. 2: v dd-out is the voltage present at the v dd pin. v dd is the internally generated bias voltage. 3: this is the total source current for all gpio pins combined. individually, each pin can source a maximum of 25 ma. 4: pe1 = 0x00h, abecon = 0x00h, atstcon = 0x80h, wpugpa = 0x00h, wpugpb = 0x00h, and sleep command issued to pic core, see section 16.0. ? 2013 microchip technology inc. ds22331a-page 23 mcp19111 current sense dc gain offset voltage i dc_offset 1.4 1.56 1.7 v voltage for zero current vzc ? 1.45 ? v vzccon = 0x80h voltage reference adjustable v out range v out_range 0.5 ? 3.6 vv out range with no external voltage divider v out coarse resolution v out_coarse 10.8 15.8 25.8 mv v out coarse mid set point v out_coarse_mid 1.85 2.04 2.25 v v out fine resolution v out_fine ?0.8 1 mv output overvoltage adjustable overvoltage range ov range 0 ? 4.5 v adjustable overvoltage mid set point ov mid 1.8 2 2.3 v adjustable overvoltage resolution ov r ? 15 ? mv output under voltage adjustable under voltage range uv range 0 ? 4.5 adjustable under volt- age mid set point uv mid 1.8 2 2.3 v adjustable under voltage resolution uv r ? 15 ? mv remote sense differential amplifier closed loop voltage gain a vol 0.95 1 1.05 v/v common mode range v cmr gnd ? 0.3 ? v dd +1.0 v note 1 common mode reject ratio cmrr ? 57 ? db differential amplifier offset v os ?40?mvsee section 9.5 ?calibration word 5? and section 9.6 ?calibration word 6? compensation minimum zero frequency f zero_min ?350?hz maximum zero frequency f zero_max ? 35000 ? hz minimum error amplifier gain g ea_min ?0?db maximum error amplifier gain g ea_max ? 36.15 ? db 4.2 electrical characteristics (continued) electrical specifications: unless otherwise noted, v in = 12v, v ref = 1.2v, f sw =300khz, t a =+25c. boldface specifications apply over the t a range of -40c to +125c. parameter symbol min typ max units conditions note 1: ensured by design. not production tested. 2: v dd-out is the voltage present at the v dd pin. v dd is the internally generated bias voltage. 3: this is the total source current for all gpio pins combined. individually, each pin can source a maximum of 25 ma. 4: pe1 = 0x00h, abecon = 0x00h, atstcon = 0x80h, wpugpa = 0x00h, wpugpb = 0x00h, and sleep command issued to pic core, see section 16.0. mcp19111 ds22331a-page 24 ? 2013 microchip technology inc. oscillator internal oscillator frequency f osc 7.60 8.00 8.40 mhz switching frequency f sw ?f osc /n ? khz switching frequency range select n 5 ? 80 maximum duty cycle ? (n?1)/n ? %/ 100 dead time adjustment dead time step size dt step ?4?ns hdrv output driver hdrv source resistance r hdrv-scr ?1 2.6 ? measured at 500 ma note 1 , high range ?2 3.5 ? measured at 500 ma note 1 , low range hdrv sink resistance r hdrv-sink ?1 2.6 ? measured at 500 ma note 1 , high range ?2 3.5 ? measured at 500 ma note 1 , low range hdrv source current i hdrv-scr ?2?a note 1 , high range ?1?a note 1 , low range hdrv sink current i hdrv-sink ?2?a note 1 , high range ?1?a note 1 , low range hdrv rise time t rh ?15 30 ns note 1 , c load =3.3nf, high range hdrv fall time t fh ?15 30 ns note 1 , c load =3.3nf, high range ldrv output driver ldrv source resistance r ldrv-scr ?1 2.5 ? measured at 500 ma note 1 ldrv sink resistance r ldrv-sink ?0.5 1.0 ? measured at 500 ma note 1 ldrv source current i ldrv-scr ?2?a note 1 ldrv sink current i ldrv-sink ?4?a note 1 ldrv rise time t rl ?15 30 ns note 1 , c load =3.3nf ldrv fall time t fl ?7 15 ns note 1 , c load =3.3nf 4.2 electrical characteristics (continued) electrical specifications: unless otherwise noted, v in = 12v, v ref = 1.2v, f sw =300khz, t a =+25c. boldface specifications apply over the t a range of -40c to +125c. parameter symbol min typ max units conditions note 1: ensured by design. not production tested. 2: v dd-out is the voltage present at the v dd pin. v dd is the internally generated bias voltage. 3: this is the total source current for all gpio pins combined. individually, each pin can source a maximum of 25 ma. 4: pe1 = 0x00h, abecon = 0x00h, atstcon = 0x80h, wpugpa = 0x00h, wpugpb = 0x00h, and sleep command issued to pic core, see section 16.0. ? 2013 microchip technology inc. ds22331a-page 25 mcp19111 linear regulator bias voltage, ldo output v dd 4.6 5.0 5.4 vv in = 6.0v to 32v, note 2 internal circuitry bias voltage av dd ? 5.0 ? vv in = 6.0v to 32v, note 2 maximum v dd output current i dd 30 ??mav in = 6.0v to 20v, v dd =5.0v, note 2 line regulation ? v dd / (v dd x ? v in ) ?0.05 0.1 %/v (v dd +1.0v) ? v in ? 20v note 2 load regulation ? v dd /v dd -1.75 -0.8 +0.5 %i dd = 1 ma to 30 ma note 2 output short circuit current i dd_sc ?65?mav in =(v dd +1.0v) note 2 dropout voltage v in ?v dd ?0.5 1 vi dd =30ma, v in =v dd +1.0v note 2 power supply rejection ratio psrr ldo ?60?dbf ? 1000 hz, i dd =25ma, c in =0f, c dd =1f band gap voltage bg -2.5% 1.23 +2.5% v gpio pins maximum gpio sink current i sink_gpio ??90ma note 3 , note 1 maximum gpio source current i source_gpio ??90ma note 3 , note 1 gpio weak pull-up current i pull-up_gpio 50 250 400 a v dd =5v gpio output low voltage v ol ??0.6vi ol =7ma, v dd =5v, t a =+90c gpio output high voltage v oh v dd ?0.7 ? ? v i oh =-2.5ma, v dd =5v, t a =+90c gpio input leakage current gpio_i il ? 0.1 1 a negative current is defined as current sourced by the pin, t a =+90c gpio input low voltage v il gnd ? 0.8 v i/o port with ttl buffer v dd =5v, t a =+90c gnd 0.2v dd v i/o port with schmitt trigger buffer, v dd =5v, t a =+90c gnd 0.2v dd vmclr , t a = +90c 4.2 electrical characteristics (continued) electrical specifications: unless otherwise noted, v in = 12v, v ref = 1.2v, f sw =300khz, t a =+25c. boldface specifications apply over the t a range of -40c to +125c. parameter symbol min typ max units conditions note 1: ensured by design. not production tested. 2: v dd-out is the voltage present at the v dd pin. v dd is the internally generated bias voltage. 3: this is the total source current for all gpio pins combined. individually, each pin can source a maximum of 25 ma. 4: pe1 = 0x00h, abecon = 0x00h, atstcon = 0x80h, wpugpa = 0x00h, wpugpb = 0x00h, and sleep command issued to pic core, see section 16.0. mcp19111 ds22331a-page 26 ? 2013 microchip technology inc. gpio input high voltage v ih 2.0 ? v dd v i/o port with ttl buffer, v dd =5v, t a =+90c 0.8v dd ?v dd v i/o port with schmitt trigger buffer, v dd =5v, t a = +90c 0.8v dd ?v dd vmclr , t a = +90c thermal shutdown thermal shutdown t shd ?160?c thermal shutdown hysteresis t shd_hys ?20?c 4.3 thermal specifications parameter symbol min typ max units test conditions temperature ranges specified temperature range t a -40 ? +125 ? c operating temperature range t a -40 ? +125 ? c maximum junction temperature t j ??+150 ? c storage temperature range t a -65 ? +150 ? c thermal package resistances thermal resistance, 28l-qfn 5x5 ? ja ?35.3? ? c/w 4.2 electrical characteristics (continued) electrical specifications: unless otherwise noted, v in = 12v, v ref = 1.2v, f sw =300khz, t a =+25c. boldface specifications apply over the t a range of -40c to +125c. parameter symbol min typ max units conditions note 1: ensured by design. not production tested. 2: v dd-out is the voltage present at the v dd pin. v dd is the internally generated bias voltage. 3: this is the total source current for all gpio pins combined. individually, each pin can source a maximum of 25 ma. 4: pe1 = 0x00h, abecon = 0x00h, atstcon = 0x80h, wpugpa = 0x00h, wpugpb = 0x00h, and sleep command issued to pic core, see section 16.0. ? 2013 microchip technology inc. ds22331a-page 27 mcp19111 5.0 digital electrical characteristics 5.1 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 5-1: load conditions 1. tpps2pps 3. t cc : st (i 2 c specifications only) 2. tpps 4. ts (i 2 c specifications only) t f frequency ttime lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdi sc sck do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall p period hhigh r rise i invalid (high-impedance) v valid l low z high-impedance i 2 c only aa output access high high buf bus free low low t cc : st (i 2 c specifications only) cc hd hold su setup st dat data input hold sto stop condition sta start condition v dd /2 c l r l pin pin v ss v ss c l r l = 464 ? c l = 50 pf for all gpio pins load co ndition 1 load co ndition 2 mcp19111 ds22331a-page 28 ? 2013 microchip technology inc. 5.2 ac characteristics: mcp19111 (industrial, extended) figure 5-2: extern al clock timing figure 5-3: clkout and i/o timing table 5-1: external clock timing requirements param no. sym characteristic min typ ? max units conditions f osc oscillator frequency ( 1 ) ?8 ?mhz 1t osc oscillator period ( 1 ) ? 250 ? ns 2t cy instruction cycle time ( 1 ) ? 1000 ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at v in =12v (v dd = 5v), +25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. osc q4 q1 q2 q3 q4 q1 1 2 osc i/o pin (input) i/o pin (output) q4 q1 q2 q3 17 20, 21 22 23 19 18 15 old value new value ? 2013 microchip technology inc. ds22331a-page 29 mcp19111 figure 5-4: reset, watchdog timer, os cillator start-up timer and power-up timer timing table 5-2: clkout and i/o timing requirements param no. sym characteristic min typ ? max units conditions 17 tosh2iov osc1 ? (q1 cycle) to ? 50 150 * ns port out valid ? ? 300 ns 18 tosh2ioi osc1 ? (q2 cycle) to port input invalid (i/o in hold time) 100 ? ? ns 19 tiov2osh port input valid to osc1 ?? (i/o in setup time) 0??ns 20 tior port output rise time ? 10 40 ns 21 tiof port output fall time ? 10 40 ns 22 22a tinp int pin high or low time 25 40 ? ? ? ? ns ns 23 23a trbp trbp port a change int high or low time tc y ? ? n s * these parameters are characterized but not tested. ? data in ?typ? column is at v in =12v (v dd =5v), +25 ? c unless otherwise stated. v dd mclr internal por pwrt time-out osc time-out internal reset watchdog timer reset 33 32 30 31 34 i/o pins 34 mcp19111 ds22331a-page 30 ? 2013 microchip technology inc. figure 5-5: timer0 and time r1 external clock timings table 5-3: reset, watchdog timer, oscill ator start-up timer, and power-up timer requirements param no. sym characteristic min typ ? max units conditions 30 t mcl mclr pulse width (low) 2 ? ? s v dd = 5v, -40c to +85c 31 t wdt watchdog timer time-out period (no prescaler) 71833msv dd = 5v, -40c to +85c 32 t ost oscillation start-up timer period ? 1024t osc ??t osc = osc1 period 33* t pwrt power up timer period (4 x t wdt ) 28 64 132 ms v dd = 5v, -40c to +85c 34 t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0s * these parameters are characterized but not tested. ? data in ?typ? column is at v in =12v (v dd = 5v), +25c unless otherwise stated. these parameters are for design guidance only and are not tested. table 5-4: timer0 and timer1 external clock requirements param no. sym characteristic min typ ? max units conditions 40 * tt0h t0cki high pulse width no prescaler 0.5t cy + 20 ? ? ns with prescaler 10 ? ? ns 41 * tt0l t0cki low pulse width no prescaler 0.5t cy + 20 ? ? ns with prescaler 10 ? ? ns 42 * tt0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) * these parameters are characterized but not tested. ? data in ?typ? column is at v in =12v (v dd = 5v), +25c unless otherwise stated. these parameters are for design guidance only and are not tested. 41 42 40 t0cki ? 2013 microchip technology inc. ds22331a-page 31 mcp19111 figure 5-6: pwm timing table 5-5: pwm requirements param no. sym characteristic min typ? max units conditions 53* tccr pwm (clkpin) output rise time ? 10 25 ns 54* tccf pwm (clkpin) output fall time ? 10 25 ns * these parameters are characterized but not tested. ? data in ?typ? column is at v in =12v (v dd = 5v), +25c unless otherwise stated. parameters are for design guidance only and are not tested. table 5-6: mcp19111 a/d converter (adc) characteristics : standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym characteristic min typ ? max unit s conditions ad01 n r resolution ? ? 10 bit ad02 e il integral error ? ? ? 1lsbav dd =5.0v ad03 e dl differential error ? ? ? 1 lsb no missing codes to 10 bits av dd =5.0v ad04 e off offset error ? +3.0 +5.0 lsb av dd =5.0v ad07 e gn gain error ? ? 2 ? 5lsbav dd =5.0v ad06 ad06a v ref reference voltage ( 3 ) ?av dd ?v ad07 v ain full-scale range gnd ? av dd v ad08 z ain recommended impedance of analog voltage source ?? 10k ? * these parameters are characterized but not tested. ? data in ?typ? column is at v in = 12v (v dd = 5v), +25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: when adc is off, it will not consume any current other than leakage current. the power-down current specification includes any such leakage from the adc module. note: refer to figure 5-1 for load conditions. 53 54 pwm (clkpin) mcp19111 ds22331a-page 32 ? 2013 microchip technology inc. figure 5-7: a/d conversion timing (normal mode) table 5-7: mcp19111 a/d conversion requirements standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym characteristic min typ ? max units conditions ad130* t ad a/d clock period 1.6 ? 9.0 s t osc -based, v ref ?? 3.0v 3.0 ? 9.0 s t osc -based, v ref full range a/d internal rc oscillator period 3.0 6.0 9.0 s adcs<1:0> = 11 (adrc mode) at v dd = 2.5v 1.6 4.0 6.0 s at v dd = 5.0v ad131 t cnv conversion time (not including acquisition time) ( 1 ) ?11?t ad set go/done bit to new data in a/d result register ad132* t acq acquisition time 11.5 ? s ad133* t amp amplifier settling time ? ? 5 s ad134 t go q4 to a/d clock start ? ? t osc /2 t osc / 2+t cy ? ? ? ? if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. * these parameters are characterized but not tested. ? data in ?typ? column is at v in =12v (v dd = 5v), +25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: adresh and adresl registers may be read on the following t cy cycle. 131 130 132 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 987 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1/2 t cy 6 134 ? 2013 microchip technology inc. ds22331a-page 33 mcp19111 figure 5-8: a/d conversion timing (sleep mode) 131 130 bsf adcon0, go q4 a/d clk a/d data adres adif go sample old_data sampling stopped done new_data 973210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 134 6 8 132 mcp19111 ds22331a-page 34 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 35 mcp19111 6.0 configuring the mcp19111 the mcp19111 is an analog controller with digital peripheral. this means that device configuration is handled through register settings instead of adding external components. the following sections detail how to set the analog control registers. 6.1 input under voltage lockout the vinlvl register contains the digital value that sets the input under voltage lockout. when the input voltage on the v in pin to the mcp19111 is below this pro- grammed level, the intcon mcp19111 ds22331a-page 36 ? 2013 microchip technology inc. 6.2 output overcurrent the mcp19111 features a cycle-by-cycle peak current limit. by monitoring the ocif interrupt flag, custom overcurrent fault handling can be implemented. to detect an output overcurrent, the mcp19111 senses the voltage drop across the high-side mosfet while it is conducting. leading edge blanking is incorporated to mask the overcurrent measurement for a given amount of time. this helps prevent false overcurrent readings. when the input voltage is greater than 20v, or if the r dson of the high-side mosfet is such that the programmed overcurrent threshold does not produce acceptable peak overcurrent protection, an alternative method must be used to determine an output overcurrent situation. an alternative technique can use the configurable output under voltage protection and the pe1 ? 2013 microchip technology inc. ds22331a-page 37 mcp19111 register 6-2: occon: output overcurrent control register r/w-0 r/w-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ocen ocleb1 ocleb0 ooc4 ooc3 ooc2 ooc1 ooc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ocen: output overcurrent dac control bit 1 = output overcurrent dac is enabled 0 = output overcurrent dac is disabled bit 6-5 ocleb<1:0>: leading edge blanking 00 = 114 ns blanking 01 = 213 ns blanking 10 = 400 ns blanking 11 = 780 ns blanking bit 4-0 ooc<4:0>: output overcurrent configuration bits 00000 = 160 mv drop 00001 = 175 mv drop 00010 = 190 mv drop 00011 = 205 mv drop 00100 = 220 mv drop 00101 = 235 mv drop 00110 = 250 mv drop 00111 = 265 mv drop 01000 = 280 mv drop 01001 = 295 mv drop 01010 = 310 mv drop 01011 = 325 mv drop 01100 = 340 mv drop 01101 = 355 mv drop 01110 = 370 mv drop 01111 = 385 mv drop 10000 = 400 mv drop 10001 = 415 mv drop 10010 = 430 mv drop 10011 = 445 mv drop 10100 = 460 mv drop 10101 = 475 mv drop 10110 = 490 mv drop 10111 = 505 mv drop 11000 = 520 mv drop 11001 = 535 mv drop 11010 = 550 mv drop 11011 = 565 mv drop 11100 = 580 mv drop 11101 = 595 mv drop 11110 = 610 mv drop 11111 = 625 mv drop mcp19111 ds22331a-page 38 ? 2013 microchip technology inc. 6.3 current sense ac gain the current measured across the inductor is a square wave that is averaged by the capacitor (c s ) connected between +i sen and -i sen . this very small voltage plus the ripple can be amplified by the current sense ac gain circuitry. the amount of gain is controlled by the csgscon register. register 6-3: csgscon: current sense ac gain control register u-0 r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ? reserved reserved reserved csgs3 csgs2 csgs1 csgs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 reserved bit 3-0 csgs<3:0>: current sense ac gain setting bits 0000 = 0 db 0001 = 1.0 db 0010 = 2.5 db 0011 = 4.0 db 0100 = 5.5 db 0101 = 7.0 db 0110 = 8.5 db 0111 = 10.0 db 1000 = 11.5 db 1001 = 13.0 db 1010 = 14.5 db 1011 = 16.0 db 1100 = 17.5 db 1101 = 19.0 db 1110 = 20.5 db 1111 = 22.0 db ? 2013 microchip technology inc. ds22331a-page 39 mcp19111 6.4 current sense dc gain dc gain can be added to the sensed inductor current to allow it to be read by the adc. the amount of dc gain added is controlled by the csdgcon register. adding dc gain to the current sense signal used by the control loop may also be needed in some multi-phase systems to account for device and component differences. the csdgen bit determines if the gained current sense signal is added back to the ac current signal (see register 6-4 ). if the csdgen bit is cleared, dc gain can still be added, but the gained signal is not added back to the ac current signal. register 6-4: csdgcon: current sense dc gain control register r/w-0 u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x csdgen ? ? ? reserved csdg2 csdg1 csdg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 csdgen: current sense dc gain enable bit 1 = dc gain current sense signal used in control loop. 0 = dc gain current sense signal only read by adc. bit 6-4 unimplemented: read as ? 0 ? bit 3 reserved bit 2-0 csdg<2:0>: current sense dc gain setting bits 000 = 19.5 db 001 = 21.8 db 010 = 24.1 db 011 = 26.3 db 100 = 28.6 db 101 = 30.9 db 110 = 33.2 db 111 = 35.7 db mcp19111 ds22331a-page 40 ? 2013 microchip technology inc. 6.5 voltage for zero current in multi-phase systems it may be necessary to provide some offset to the sensed inductor current. the vzccon register can be used to provide a positive or negative offset in the sensed current. typically, the vzccon will be set to 0x80h, which corresponds to the sensed inductor current centered around 1.45v. however, by adjusting the vzccon register, this centered voltage can be shifted up or down by approximately 3.28 mv per step. register 6-5: vzccon: voltage for zero current control register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x vzc7 vzc6 vzc5 vzc4 vzc3 vzc2 vzc1 vzc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 vzc<7:0>: voltage for zero current setting bits 00000000 = -420.00 mv offset 00000001 = -416.72 mv offset ? ? ? 10000000 = 0 mv offset ? ? ? 11111110 = +413.12 mv offset 11111111 = +416.40 mv offset ? 2013 microchip technology inc. ds22331a-page 41 mcp19111 6.6 compensation setting the mcp19111 uses a peak current mode control architecture. a control reference is used to regulate the peak current of the converter directly. the inner current loop essentially turns the inductor into a voltage- controlled current source. this reduces the control-to- output transfer function to a simple single-pole model of a current source feeding a capacitor. the desired response of the overall loop can be tuned by proper placement of the compensation zero frequency and gain. figure 6-1 shows a simplified drawing of the internal compensation. see register 6-6 for the adjustable zero frequency and gain settings. figure 6-1: simplified compensation v ref +v sen -v sen register 6-6 cmpzcon compensation setting control register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x cmpzf3 cmpzf2 cmpzf1 cmpzf0 cmpzg3 cmpzg2 cmpzg1 cmpzg0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 cmpzf<3:0>: compensation zero frequency setting bits 0000 = 1500 hz 0001 = 1850 hz 0010 = 2300 hz 0011 = 2840 hz 0100 = 3460 hz 0101 = 4300 hz 0110 = 5300 hz 0111 = 6630 hz 1000 = 8380 hz 1001 = 9950 hz 1010 = 12200 hz 1011 = 14400 hz 1100 = 18700 hz 1101 = 23000 hz 1110 = 28400 hz 1111 = 35300 hz bit 3-0 cmpzg<3:0>: compensation gain setting bits 0000 = 36.15 db 0001 = 33.75 db 0010 = 30.68 db 0011 = 28.43 db 0100 = 26.10 db 0101 = 23.81 db 0110 = 21.44 db 0111 = 19.10 db 1000 = 16.78 db 1001 = 14.32 db 1010 = 12.04 db 1011 = 9.54 db 1100 = 7.23 db 1101 = 4.61 db 1110 = 2.28 db 1111 = 0.00 db mcp19111 ds22331a-page 42 ? 2013 microchip technology inc. 6.7 slope compensation a negative voltage slope is added to the output of the error amplifier. this is done to prevent subharmonic instability when: 1. the operating duty cycle is greater than 50% 2. wide changes in the duty cycle occur. the amount of negative slope added to the error ampli- fier output is controlled by register 6-7 . the slope compensation is enabled by setting the slcpby bit in the abecon register. 6.7.1 slps<3:0> configuration the slps<3:0> directly controls the ? v/ ? t of the added ramp. this byte should be set proportional to the switching frequency according to the following equation. 6.7.2 slpg<3:0> configuration the slpg<3:0> controls the amplitude of the added ramp. the values listed above correspond to a 50% duty cycle waveform and is true only if the slps<3:0> bits are set according to the equation in section 6.7.1 ?slps<3:0> configuration? . if less amplitude is required, the slps<3:0> bits can be adjusted to a lower switching frequency. register 6-7: slpcrcon: slope co mpensation ramp control register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x slpg3 slpg2 slpg1 slpg0 slps3 slps2 slps1 slps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 slpg<3:0>: slope compensation amplitude configuration bits 0000 = 0.017 v pk-pk , measured for 50% duty cycle waveform 0001 = 0.022 v pk-pk , measured for 50% duty cycle waveform 0010 = 0.030 v pk-pk , measured for 50% duty cycle waveform 0011 = 0.040 v pk-pk , measured for 50% duty cycle waveform 0100 = 0.053 v pk-pk , measured for 50% duty cycle waveform 0101 = 0.070 v pk-pk , measured for 50% duty cycle waveform 0110 = 0.094 v pk-pk , measured for 50% duty cycle waveform 0111 = 0.125 v pk-pk , measured for 50% duty cycle waveform 1000 = 0.170 v pk-pk , measured for 50% duty cycle waveform 1001 = 0.220 v pk-pk , measured for 50% duty cycle waveform 1010 = 0.300 v pk-pk , measured for 50% duty cycle waveform 1011 = 0.400 v pk-pk , measured for 50% duty cycle waveform 1100 = 0.530 v pk-pk , measured for 50% duty cycle waveform 1101 = 0.700 v pk-pk , measured for 50% duty cycle waveform 1110 = 0.940 v pk-pk , measured for 50% duty cycle waveform 1111 = 1.250 v pk-pk , measured for 50% duty cycle waveform bit 3-0 slps<3:0>: slope compensation ? v/ ? t configuration bits n f sw 100 000 ? -------------------- - ?? ?? 1 ? = where: f sw = device switching frequency n = decimal equivalent of slps<3:0> ? 2013 microchip technology inc. ds22331a-page 43 mcp19111 6.8 master error signal gain when operating in a multi-phase system, the output of the master?s error amplifier is used by all slave devices as their control signal. it is important to balance the current in all phases to maintain a uniform temperature across all phases. component tolerances make this balancing difficult. each slave device has the ability to gain or attenuate the master error signal depending upon the settings of register 6-8 . note: the slvgncon register is configured in the multi-phase slave device. register 6-8: slvgncon: master error signal input gain control register u-0 u-0 u-0 r/w-x r/w-x r/w-x r/w-x r/w-x ? ? ? slvgn4 slvgn3 slvgn2 slvgn1 slvgn0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4-0 slvgn<4:0>: master error signal gain bits 00000 = -3.3 db 00001 = -3.1 db 00010 = -2.9 db 00011 = -2.7 db 00100 = -2.5 db 00101 = -2.3 db 00110 = -2.1 db 00111 = -1.9 db 01000 = -1.7 db 01001 = -1.4 db 01010 = -1.2 db 01011 = -1.0 db 01100 = -0.8 db 01101 = -0.6 db 01110 = -0.4 db 01111 = -0.2 db 10000 = 0.0 db 10001 = 0.2 db 10010 = 0.4db 10011 = 0.7 db 10100 = 0.9 db 10101 = 1.1 db 10110 = 1.3 db 10111 = 1.5 db 11000 = 1.7 db 11001 = 1.9 db 11010 = 2.1 db 11011 = 2.3 db 11100 = 2.6 db 11101 = 2.8 db 11110 = 3.0 db 11111 = 3.2 db mcp19111 ds22331a-page 44 ? 2013 microchip technology inc. 6.9 mosfet driver programmable dead time the turn-on delay of the high-side and low-side drive signals can be configured independently to allow differ- ent mosfets and circuit board layouts to be used to construct an optimized system. see figure 6-2 . setting the hdlyby and ldlyby bits of the pe1 register enables the high-side and low-side delay, respectively. the amount of delay added is controlled in the deadcon register. see register 6-9 for more information. figure 6-2: mosfet driver dead time hdly ldly hdrv ldrv register 6- deadcon driver dead time control register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x hdly3 hdly2 hdly1 hdly0 ldly3 ldly2 ldly1 ldly0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 hdly<3:0>: high-side dead time configuration bits 0000 = 11 ns delay 0001 = 15 ns delay 0010 = 19 ns delay 0011 = 23 ns delay 0100 = 27 ns delay 0101 = 31 ns delay 0110 = 35 ns delay 0111 = 39 ns delay 1000 = 43 ns delay 1001 = 47 ns delay 1010 = 51 ns delay 1011 = 55 ns delay 1100 = 59 ns delay 1101 = 63 ns delay 1110 = 67 ns delay 1111 = 71 ns delay bit 3-0 ldly<3:0>: low-side dead time configuration bits 0000 = 4 ns delay 0001 = 8 ns delay 0010 = 12 ns delay 0011 = 16 ns delay 0100 = 20 ns delay 0101 = 24 ns delay 0110 = 28 ns delay 0111 = 32 ns delay 1000 = 36 ns delay 1001 = 40 ns delay 1010 = 44 ns delay 1011 = 48 ns delay 1100 = 52 ns delay 1101 = 56 ns delay 1110 = 60 ns delay 1111 = 64 ns delay ? 2013 microchip technology inc. ds22331a-page 45 mcp19111 6.10 output voltage configuration two registers control the error amplifier reference voltage. the reference is coarsely set in 15 mv steps and then finely adjusted in 0.82 mv steps above the coarse setting (see registers 6-10 and 6-11 ). higher output voltages can be achieved by using a voltage divider connected between the output and the +v sen pin. care must be taken to ensure maximum voltage rating compliance on all pins. note: the ovfcon mcp19111 ds22331a-page 46 ? 2013 microchip technology inc. 6.11 output under voltage the output voltage is monitored, and when it is below the output under voltage threshold, the uvif flag is set. this flag must be cleared in software. see section 15.3.1.4 ?pir2 register? for more information. the output under voltage threshold is controlled by the ouvcon register, as shown in register 6-12 . 6.12 output overvoltage the output voltage is monitored, and when it is above the output over voltage threshold, the ovif flag is set. this flag must be cleared in software. see section 15.3.1.4 ?pir2 register? for more information. the output over voltage threshold is controlled by the oovcon register, as shown in register 6-13 . register 6-12: ouvcon: output under vo ltage detect level control register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x ouv7 ouv6 ouv5 ouv4 ouv3 ouv2 ouv1 ouv0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 ouv<7:0>: output under voltage detect level configuration bits ouv<7:0> = (v out_uv_detect_level )/15 mv register 6-13: oovcon: output overvo ltage detect level control register r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x r/w-x oov7 oov6 oov5 oov4 oov3 oov2 oov1 oov0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 oov<7:0>: output overvoltage detect level configuration bits oov<7:0> = (v out_ov_detect_level )/15 mv ? 2013 microchip technology inc. ds22331a-page 47 mcp19111 6.13 analog peripheral control the mcp19111 has various analog peripherals. these peripherals can be configured to allow customizable operation. refer to register 6-14 more information. 6.13.1 diode emulation mode the mcp19111 can operate in either diode emulation or synchronous rectification mode. when operating in diode emulation mode, the ldrv signal is terminated when the voltage across the low-side mosfet is approximately 0v. this condition is true when the inductor current reaches approximately 0a. both the hdrv and ldrv signals are low until the beginning of the next switching cycle. at that time, the hdrv signal is asserted high, turning on the high-side mosfet. when operating in synchronous rectification mode, the ldrv signal is held high until the beginning of the next switching cycle. at that time, the hdrv signal is asserted high, turning on the high-side mosfet. the pe1 mcp19111 ds22331a-page 48 ? 2013 microchip technology inc. register 6-14: pe1: analog periph eral enable 1 control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 decon dvrstr hdlyby ldlyby pden puen uvtee ovtee bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 decon: diode emulation mode bit 1 = diode emulation mode enabled 0 = synchronous rectification mode enabled bit 6 dvrstr: high-side drive strength configuration bit 1 = high-side 1a source/sink drive strength 0 = high-side 2a source/sink drive strength bit 5 hdlyby: high-side dead time bypass bit 1 = high-side dead time bypass is enabled 0 = high-side dead time bypass is disabled bit 4 ldlyby: low-side dead time bypass bit 1 = low-side dead time bypass is enabled 0 = low-side dead time bypass is disabled bit 3 pden: -v sen weak pull down enable bit 1 = -v sen weak pull down is enabled 0 = -v sen weak pull down is disabled bit 2 puen: +v sen weak pull up enable bit 1 = +v sen weak pull up is enabled 0 = +v sen weak pull up is disabled bit 1 uvtee: output under voltage accelerator enable bit 1 = output under voltage accelerator is enabled 0 = output under voltage accelerator is disabled bit 0 ovtee: output over voltage accelerator enable bit 1 = output over voltage accelerator is enabled 0 = output over voltage accelerator is disabled ? 2013 microchip technology inc. ds22331a-page 49 mcp19111 6.14 analog blocks enable control various analog circuit blocks can be enabled or disabled, as shown in register 6-15 . addition enable bits are located in the atstcon register. 6.14.1 output overvoltage enable the output overvoltage is enabled by setting the abecon mcp19111 ds22331a-page 50 ? 2013 microchip technology inc. register 6-15: abecon: analog block enable control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ovdcen uvdcen measen slcpby crtmen tmpsen reciren pathen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 ovdcen: output over voltage dac control bit 1 = output over voltage dac is enabled 0 = output over voltage dac is disabled bit 6 uvdcen: output under voltage dac control bit 1 = output under voltage dac is enabled 0 = output under voltage dac is disabled bit 5 measen: relative efficiency measurement control bit 1 = initiate relative efficiency measurement 0 = relative efficiency measurement not in progress bit 4 slcpby: slope compensation bypass control bit 1 = slope compensation is disabled 0 = slope compensation is enabled bit 3 crtmen: current measurement circuitry control bit 1 = current measurement circuitry is enabled 0 = current measurement circuitry is disabled bit 2 tmpsen: internal temperature sensor control bit 1 = internal temperature sensor circuitry is enabled 0 = internal temperature sensor circuitry is disabled bit 1 reciren: relative efficiency circuitry control bit 1 = relative efficiency measurement circuitry is enabled 0 = relative efficiency measurement circuitry is disabled bit 0 pathen: signal chain circuitry control bit 1 = signal chain circuitry is enabled 0 = signal chain circuitry is disabled ? 2013 microchip technology inc. ds22331a-page 51 mcp19111 7.0 typical performance curves note: unless otherwise indicated, v in = 12v, f sw = 300 khz, t a = +25c. figure 7-1: i q vs. temperature. figure 7-2: ovccon dac inl vs. code and temperature (-40c to +125c). figure 7-3: ovccon dac dnl vs. code and temperature (-40c to +125c). figure 7-4: ovfcon dac inl vs. code and temperature (-40c to +125c). figure 7-5: ovfcon dac dnl vs. code and temperature (-40c to +125c). figure 7-6: v dd vs. input voltage. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range. 4.8 5.0 5.2 5.4 5.6 c ent current (ma) 4.2 4.4 4.6 -40 -25 -10 5 20 35 50 65 80 95 110 125 quies c temperature (oc) -0.6 -0.4 -0.2 0.0 0.2 inl (lsb) -1.2 -1.0 -0.8 0 64 128 192 256 code 0.015 0.020 0.025 0.030 dnl (lsb) 0.005 0.010 0 64 128 192 256 code -0.2 0.0 0.2 0.4 0.6 0.8 1.0 inl (lsb) -1.0 -0.8 -0.6 -0.4 02468101214161820222426283032 code 0.0006 0.0008 0.0010 0.0012 0.0014 0.0016 dnl (lsb) 0.0000 0.0002 0.0004 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 code 5.06 5.07 5.08 5.09 v dd (v) -40oc +125oc i dd = 1 ma 5.04 5.05 6 8 10 12 14 16 18 20 22 24 26 28 30 32 input voltage, v in (v) +25oc mcp19111 ds22331a-page 52 ? 2013 microchip technology inc. note: unless otherwise indicated, v in = 12v, f sw = 300 khz, t a = +25c. figure 7-7: v dd vs. output current. figure 7-8: v regref vs. temperature (v regref = 0.6v). figure 7-9: v regref vs. temperature (v regref = 1.8v). figure 7-10: v regref vs. temperature (v regref = 3.3v). figure 7-11: hdrv dead time vs. hdly code. figure 7-12: ldrv dead time vs. ldly code. 5.02 5.03 5.04 5.05 5.06 5.07 v dd (v) - 40oc +125oc +25oc 4.99 5.00 5.01 024681012141618202224262830 current (ma) 059 0.60 0.61 0.62 0.63 v regref (v) ovccon = 0x28h 0.57 0.58 0 . 59 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) 1.80 1.81 1.82 1.83 1.84 v regref (v) ovccon = 0x78h 1.77 1.78 1.79 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) 3.29 3.30 3.31 3.32 3.33 3.34 3.35 v regref (v) ovccon = 0xdch 3.25 3.26 3.27 3.28 -40 -25 -10 5 20 35 50 65 80 95 110 125 temperature (oc) 40 50 60 70 80 d rv dead time (ns) -40oc 125oc 10 20 30 0 2 4 6 8 10 12 14 16 h d hdly code + 125oc +25oc 30 40 50 60 70 r v dead time (ns) +125oc +25oc 0 10 20 0246810121416 ld r ldly code -40oc ? 2013 microchip technology inc. ds22331a-page 53 mcp19111 note: unless otherwise indicated, v in = 12v, f sw = 300 khz, t a = +25c. figure 7-13: hdrv r dson vs. temperature. figure 7-14: hdrv r dson vs. temperature. figure 7-15: ldrv r dson vs. temperature. figure 7-16: oscillator frequency vs. temperature. figure 7-17: crnt voltage vs. output current. figure 7-18: remote sense amplifier cmrr. 0.8 0.9 1.0 1.1 1.2 1.3 1.4 r v resistance () drvstr = 0 r hdrv-source 0.4 0.5 0.6 0.7 -40-25-10 5 203550658095110125 hd r temperature (oc) r hdrv-sink 1.5 2.0 2.5 3.0 r v resistance () drvstr = 1 r hdrv-source 0.5 1.0 -40-25-10 5 203550658095110125 hd r temperature (oc) r hdrv-sink 0.8 1.0 1.2 1.4 1.6 r v resistance ( ) r ldrv-source 0.2 0.4 0.6 -40-25-10 5 203550658095110125 ld r temperature (oc) r ldrv-sink 7.99 8.00 8.01 8.02 8.03 8.04 8.05 t or frequency (mhz) 7.95 7.96 7.97 7.98 -40-25-10 5 203550658095110125 oscilla t temperature (oc) 1.57 1.58 1.59 1.60 1.61 1.62 1.63 1.64 r nt voltage (v) r ind = 3.0 m 1.53 1.54 1.55 1.56 0 5 10 15 20 25 30 c r output current (a) 8% 10% 12% 14% 16% 18% 20% 22% 24% n tage of occurences 0% 2% 4% 6% 8% 30 38 47 56 64 73 81 90 100 perce n cmrr (db) mcp19111 ds22331a-page 54 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 55 mcp19111 8.0 system bench testing to allow for easier system design and bench testing, the mcp19111 device features a multiplexer used to output various internal analog signals. these signals can be measured on the gpa0 pin through a unity gain buffer. the configuration control of the gpa0 pin is found in the atstcon register, as shown in register 8-1 . control of the signals present at the output of the unity gain buffer is found in the buffcon register, as shown in register 8-2 . 8.1 analog bench test control 8.1.1 atstcon register the atstcon register contains the bits used to dis- able the mosfet drivers and configure the gpa0 pin as the unity gain buffer out, as shown in register 8-1 . note 1: the drvdis bit is reset to ? 1 ? so the high- side and low-side drivers are in a known state after reset. this bit must be cleared by software for normal operation. register 8-1: atstcon: analog bench test control register r/w-1 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-1 reserved ? ? reserved hidis lodis bnchen drvdis bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 reserved bit 6-5 unimplemented: read as ? 0 ? bit 4 reserved bit 3 hidis: high-side driver control bit 1 = high-side driver is disabled 0 = high-side driver is enabled bit 2 lodis: low-side driver control bit 1 = low-side driver is disabled 0 = low-side driver is enabled bit 1 bnchen: gpa0 bench test configuration control bit 1 = gpa0 is configured for analog bench test output 0 = gpa0 is configured for normal operation bit 0 drvdis: mosfet driver disable control bit 1 = high-side and low-side drivers are set low, phase pin is floating 0 = high-side and low-side drivers are set for normal operation mcp19111 ds22331a-page 56 ? 2013 microchip technology inc. 8.2 unity gain buffer the unity gain buffer module is used during a multi- phase application and while operating in bench test mode. when the atstcon ? 2013 microchip technology inc. ds22331a-page 57 mcp19111 9.0 device calibration read-only memory locations 2080h through 208fh contain factory calibration data. refer to section 18.0 ?flash program memory control? for information on how to read from these memory locations. 9.1 calibration word 1 the dov<3:0> bits at memory location 2080h set the offset calibration for the output voltage remote sense differential amplifier. firmware must read these values and write them to the dovcal register for proper calibration. the fcal<6:0> bits at memory location 2080h set the internal oscillator calibration. firmware must read these values and write them to the osccal register for proper calibration. register 9-1: calwd1: calibration word 1 register u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? dov3 dov2 dov1 dov0 bit 13 bit 8 u-0 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 ? fcal6 fcal5 fcal4 fcal3 fcal2 fcal1 fcal0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-12 unimplemented: read as ? 0 ? bit 11-8 dov<3:0>: output voltage remote sense differential amplifier offset calibration bits. bit 7 unimplemented: read as ? 0 ? bit 6-0 fcal<6:0>: internal oscillator calibration bits. mcp19111 ds22331a-page 58 ? 2013 microchip technology inc. 9.2 calibration word 2 the tta<3:0> bits at memory location 2082h calibrate the overtemperature shutdown threshold point. firm- ware must read these values and write them to the ttacal register for proper calibration. the bgr<3:0> bits at memory location 2082h calibrate the internal band gap. firmware must read these values and write them to the bgrcal register for proper calibration. register 9-2: calwd2: calibration word 2 register u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? tta3 tta2 tta1 tta0 bit 13 bit 8 u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? bgr3 bgr2 bgr1 bgr0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-12 unimplemented: read as ? 0 ? bit 11-8 tta<3:0>: overtemperature shutdown threshold calibration bits. bit 7-4 unimplemented: read as ? 0 ? bit 3-0 bgr<3:0>: internal band gap calibration bits. ? 2013 microchip technology inc. ds22331a-page 59 mcp19111 9.3 calibration word 3 the vro<3:0> bits at memory location 2083h calibrate the offset of the buffer amplifier of the output voltage regulation reference set point. this effectively changes the band gap reference. firmware must read these values and write them to the vrocal register for proper calibration. the zro<3:0> bits at memory location 2083h calibrate the offset of the error amplifier. firmware must read these values and write them to the zrocal register for proper calibration. register 9-3: calwd3: calibration word 3 register u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? vro3 vro2 vro1 vro0 bit 13 bit 8 u-0 u-0 u-0 u-0 r/p-1 r/p-1 r/p-1 r/p-1 ? ? ? ? zro3 zro2 zro1 zro0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-12 unimplemented: read as ? 0 ? bit 11-8 vro<3:0>: reference voltage offset calibration bits. bit 7-4 unimplemented: read as ? 0 ? bit 3-0 zro<3:0>: error amplifier offset voltage calibration bits. mcp19111 ds22331a-page 60 ? 2013 microchip technology inc. 9.4 calibration word 4 the tana<9:0> bits at memory location 2084h contain the adc reading from the internal temperature sensor when the silicon temperature is at +30c. the temperature coefficient of the internal temperature sensor is 16 mv/c. register 9-4: calwd4: calibration word 4 register u-0 u-0 u-0 u-0 r/p-1 r/p-1 ? ? ? ? tana9 tana8 bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 tana7 tana6 tana5 tana4 tana3 tana2 tana1 tana0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-10 unimplemented: read as ? 0 ? bit 9-0 tana<9:0>: adc internal temperature sensor at +30c calibration bits tana<9:0> = (temperature x 13.3 mv/c) +1.75 ? 2013 microchip technology inc. ds22331a-page 61 mcp19111 9.5 calibration word 5 the difc<7:0> bits at memory location 2085h contain the offset voltage information for the output voltage difference amplifier. the value is an 8-bit two?s complement number that represents the number of the ovccon counts needed to adjust for the differential amplifier offset. this value can be used to completely remove the differential amplifier offset. for example, the offset of the differential amplifier is measured to be -64 mv. since one ovccon count equals 16 mv, this represents 4 counts of the ovccon register. therefore, the value stored at location 2085h would be 0x84h, where the setting of the difc7 bit represents a negative number. register 9-5: calwd5: calibration word 5 register u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 difc7 difc6 difc5 difc4 difc3 difc2 difc1 difc0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-8 unimplemented: read as ? 0 ? bit 7-0 difc<7:0>: ovccon counts to adjust for differential amplifier offset calibration bits mcp19111 ds22331a-page 62 ? 2013 microchip technology inc. 9.6 calibration word 6 the diff<7:0> bits at memory location 2086h contain the offset voltage information for the output voltage difference amplifier. the value is an 8-bit two?s complement number that represents the number of the ovfcon counts needed to adjust for the differential amplifier offset. this value can be used to completely remove the differential amplifier offset. for example, the offset of the differential amplifier is measured to be +4.2 mv. since one ovfcon count equals 0.7 mv, this represents six counts of the ovfcon register. therefore the value stored at location 2086h would be 0x06h, where clearing the diff7 bit represents a positive number. register 9-6: calwd6: calibration word 6 register u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 diff7 diff6 diff5 diff4 diff3 diff2 diff1 diff0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-8 unimplemented: read as ? 0 ? bit 7-0 diff<7:0>: ovfcon counts to adjust for differential amplifier offset calibration bits ? 2013 microchip technology inc. ds22331a-page 63 mcp19111 9.7 calibration word 7 the buff<7:0> bits at memory location 2087h represent the offset voltage of the unity gain buffer. this is an 8-bit two?s complement number. the msb is the sign bit. if the msb is set to 1, the resulting number is negative. register 9-7: calwd7: calibration word 7 register u-0 u-0 u-0 u-0 u-0 u-0 ? ? ? ? ? ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 buff7 buff6 buff5 buff4 buff3 buff2 buff1 buff0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-8 unimplemented: read as ? 0 ? bit 7-0 buff<7:0>: unity gain buffer offset voltage calibration bits mcp19111 ds22331a-page 64 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 65 mcp19111 10.0 relative efficiency measurement with a constant input voltage, output voltage and load current, any change in the high-side mosfet on-time represents a change in the system efficiency. the mcp19111 is capable of measuring the on-time of the high-side mosfet. therefore, the relative efficiency of the system can be measured and optimized by changing the system parameters, such as switching frequency, driver dead time or high-side drive strength. 10.1 relative efficiency measurement procedure to measure the relative efficiency, the releff regis- ter, abecon mcp19111 ds22331a-page 66 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 67 mcp19111 11.0 memory organization there are two types of memory in the mcp19111: ? program memory ? data memory - special function registers (sfrs) - general purpose ram 11.1 program memory organization the mcp19111 has a 13-bit program counter capable of addressing an 8k x 14 program memory space. only the first 4k x 14 (0000h-0fffh) is physically implemented. addressing a location above this boundary will cause a wrap-around within the first 4k x 14 space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 11-1 ). the width of the program memory bus (instruction word) is 14-bits. since all instructions are a single word, the mcp19111 has space for 4k of instructions. figure 11-1: program memory map and stack for mcp19111 unimplemented pc<12:0> 13 0000h 0004h 0005h 0fffh 1fffh stack level 1 stack level 8 reset vector interrupt vector on-chip program memory call, return retfie, retlw 1000h user ids (1) device id (hardcoded) (1) config word (1) 2000h 2005h 2006h 2007h 200ah 207fh 20ffh 2003h 2004h icd instruction (1) manufacturing codes (1) note 1: not code protected. shadows 000-fffh 2008h reserved for manufacturing & test (1) 2080h calibration words (1) 200bh 208fh 2090h shadows 2000-20ffh 2100h 3fffh reserved mcp19111 ds22331a-page 68 ? 2013 microchip technology inc. 11.1.1 reading program memory as data there are two methods of accessing constants in pro- gram memory. the first method is to use tables of retlw instructions. the second method is to set a files select register (fsr) to point to the program memory. 11.1.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to create such a table is shown in example 11-1 . example 11-1: retlw instruction 11.1.1.2 indirect read with files select register ( fsr) the program memory can be accessed as data by setting bit 7 of the fsrxh register and reading the matching indfx register. the moviw instruction will place the lower 8 bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the program memory via the fsr require one extra instruction cycle to complete. example 11-2 demonstrates accessing the program memory via an fsr. the high directive will set bit<7> if a label points to a location in program memory. example 11-2: accessing program memory via fsr 11.2 data memory organization the data memory (see figure 11-1 ) is partitioned into four banks, which contain the general purpose registers (gpr) and the special function registers (sfr). the special function registers are located in the first 32 locations of each bank. register locations 20h-7fh in bank 0, a0h-efh in bank 1 and 120h-16fh in bank 2 are general purpose registers, implemented as static ram. all other ram is unimplemented and returns ?0? when read. the rp<1:0> bits of the status register are the bank select bits. to move values from one register to another register, the value must pass throught the w register. this means that for all register-to-register moves, two instruction cycles are required. the status register, shown in register 11-1 , contains: ? the arithmetic status of the alu ? the reset status ? the bank select bits for data memory (ram) the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw data_index call constants ;? the constant is in w constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw low constants movwf fsr1l movlw high constants movwf fsr1h moviw 0[fsr1] ;the program memory is in w rp1 rp0 00 -> bank 0 is selected 01 -> bank 1 is selected 10 -> bank 2 is selected 11 -> bank 3 is selected ? 2013 microchip technology inc. ds22331a-page 69 mcp19111 for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). therefore, it is recommended that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits, see the section 29.0 ?instruction set summary? . 11.2.1 special function registers the special function registers are registers used by the cpu and peripheral functions for controlling the desired operation of the device (see table 11-1 ). these registers are static ram. the special registers can be classified into two sets: core and peripheral. the special function registers associated with the microcontroller core are described in this section. those related to the operation of the peripheral features are described in the section of that peripheral feature. note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 11-1: status: status register r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x irp rp1 rp0 to pd zdc ( 1 ) c ( 1 ) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 irp: register bank select bit (used for indirect addressing) 1 = reserved 0 = bank 0, 1, 2, 3 (00h - ffh) bit 6-5 rp<1:0>: register bank select bits (used for direct addressing) 00 = bank 0 (00h - 7fh) 01 = bank 1 (80h - ffh) 10 = bank 2 (100h - 17fh) 11 = bank 3 (180h - 1ffh) bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( 1 ) ( addwf , addlw , sublw , subwf instructions) 1 = a carry-out from the 4 th low-order bit of the result occurred 0 = no carry-out from the 4 th low-order bit of the result bit 0 c: carry/borrow bit ( 1 ) ( addwf , addlw , sublw , subwf instructions) ( 1 ) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register. mcp19111 ds22331a-page 70 ? 2013 microchip technology inc. 11.3 data memory table 11-1: mcp19111 data memory map file address file address file address file address indirect addr. ( 1 ) 00h indirect addr. ( 1 ) 80h indirect addr. ( 1 ) 100h indirect addr. ( 1 ) 180h tmr0 01h option_reg 81h tmr0 101h option_reg 181h pcl 02h pcl 82h pcl 102h pcl 182h status 03h status 83h status 103h status 183h fsr 04h fsr 84h fsr 104h fsr 184h portgpa 05h TRISGPA 85h wpugpa 105h ioca 185h portgpb 06h trisgpb 86h wpugpb 106h iocb 186h pir1 07h pie1 87h pe1 107h ansela 187h pir2 08h pie2 88h buffcon 108h anselb 188h pcon 09h apfcon 89h abecon 109h 189h pclath 0ah pclath 8ah pclath 10ah pclath 18ah intcon 0bh intcon 8bh intcon 10bh intcon 18bh tmr1l 0ch 8ch 10ch porticd ( 2 ) 18ch tmr1h 0dh 8dh 10dh trisicd ( 2 ) 18dh t1con 0eh 8eh 10eh ickbug ( 2 ) 18eh tmr2 0fh 8fh 10fh bigbug ( 2 ) 18fh t2con 10h vinlvl 90h sspadd 110h pmcon1 190h pr2 11h occon 91h sspbuf 111h pmcon2 191h 12h 92h sspcon1 112h pmadrl 192h pwmphl 13h csgscon 93h sspcon2 113h pmadrh 193h pwmphh 14h 94h sspcon3 114h pmdatl 194h pwmrl 15h csdgcon 95h sspmsk 115h pmdath 195h pwmrh 16h 96h sspstat 116h 196h 17h vzccon 97h sspadd2 117h 197h 18h cmpzcon 98h sspmsk2 118h osccal 198h ovccon 19h ouvcon 99h 119h dovcal 199h ovfcon 1ah oovcon 9ah 11ah ttacal 19ah osctune 1bh deadcon 9bh 11bh bgrcal 19bh adresl 1ch slpcrcon 9ch 11ch vrocal 19ch adresh 1dh slvgncon 9dh 11dh zrocal 19dh adcon0 1eh releff 9eh 11eh 19eh adcon1 1fh 9fh 11fh atstcon 19fh general purpose register 96 bytes 20h general purpose register 80 bytes a0h general purpose register 80 bytes 120h 1a0h efh 16f 1ef 7fh accesses bank 0 f0h ffh accesses bank 0 170h 17fh accesses bank 0 1f0h 1ffh bank 0 bank 1 bank2 bank3 unimplemented data memory locations, read as '0'. note 1: not a physical register. 2: only accessible when dbgen = 0 and ickbug ? 2013 microchip technology inc. ds22331a-page 71 mcp19111 table 11-2: mcp19111 special registers summary bank 0 adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset value on all other resets (1) bank 0 00h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 01h tmr0 timer0 module?s register xxxx xxxx uuuu uuuu 02h pcl program counter's (pc) least significant byte 0000 0000 0000 0000 03h status irp rp1 rp0 to pd zdcc 0001 1xxx 000q quuu 04h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 05h portgpa gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 xxxx xxxx uuuu uuuu 06h portgpb gpb7 gpb6 gpb5 gpb4 ? gpb2 gpb1 gpb0 xxx- xxxx uuu- uuuu 07h pir1 ? adif bclif sspif ? ?tmr2iftmr1if -000 --00 -000 --00 08h pir2 uvif ?ocifovif ? ? vinif dcerif 0-00 --00 0-00 --00 09h pcon ? ? ? ? ?ot por ? ---- -qq- ---- -uu- 0ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 0bh intcon gie peie t0ie inte ioce t0if intf iocf (3) 0000 000x 0000 000u 0ch tmr1l holding register for the least significant byte of the 16-bit tmr1 xxxx xxxx uuuu uuuu 0dh tmr1h holding register for the most significant byte of the 16-bit tmr1 xxxx xxxx uuuu uuuu 0eh t1con ? ? t1ckps1 t1ckps0 ? ? tmr1cs tmr1on --00 --00 --uu --uu 0fh tmr2 timer2 module register 0000 0000 uuuu uuuu 10h t2con ? ? ? ? ? tmr2on t2ckps1 t2ckps0 ---- -000 ---- -000 11h pr2 timer2 module period register 1111 1111 1111 1111 12h ? unimplemented ? ? 13h pwmphl slave phase shift register xxxx xxxx uuuu uuuu 14h pwmphh slave phase shift register xxxx xxxx uuuu uuuu 15h pwmrl pwm register low byte xxxx xxxx uuuu uuuu 16h pwmrh pwm register high byte xxxx xxxx uuuu uuuu 17h ? unimplemented ? ? 18h ? unimplemented ? ? 19h ovccon ovc7 ovc6 ovc5 ovc4 ovc3 ovc2 ovc1 ovc0 0000 0000 0000 0000 1ah ovfcon vouton ? ? ovf4 ovf3 ovf2 ovf1 ovf0 0--0 0000 0--0 0000 1bh osctune ? ? ? tun4 tun3 tun2 tun1 tun0 ---0 0000 ---0 0000 1ch adresl least significant 8 bits of the right-shifted result xxxx xxxx uuuu uuuu 1dh adresh most significant 2 bits of right-shifted result ---- --xx uuuu uuuu 1eh adcon0 ? chs4 chs3 chs2 chs1 chs0 go/done adon -000 0000 -000 0000 1fh adcon1 ? adcs2 adcs1 adcs0 ? ? ? ? -000 ---- -000 ---- legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: irp & rp1 bits are reserved, always maintain these bits clear. 3: mclr and wdt reset does not affect the previous value data latch. the iocf bit will be cleared upon reset but will set again if the mismatch exists. mcp19111 ds22331a-page 72 ? 2013 microchip technology inc. table 11-3: mcp19111 special registers summary bank 1 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset values on all other resets (1) bank 1 80h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 81h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 82h pcl program counter's (pc) least significant byte 0000 0000 0000 0000 83h status irp (2) rp1 (2) rp0 to pd zdcc 0001 1xxx 000q quuu 84h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISGPA trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 1111 1111 1111 1111 86h trisgpb trisb7 trisb6 trisb5 trisb4 ? trisb2 trisb1 trisb0 1111 1111 1111 1111 87h pie1 ? adie bclie sspie ? ? tmr2ie tmr1ie -000 --00 -000 --00 88h pie2 uvie ?ocieovie ? ? vinie dcerie 0-00 --00 0-00 --00 89h apfcon ? ? ? ? ? ? ? clksel ---- ---0 ---- ---0 8ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 8bh intcon gie peie t0ie inte ioce t0if intf iocf (4) 0000 000x 0000 000u 8ch ? unimplemented ? ? 8dh ? unimplemented ? ? 8eh ? unimplemented ? ? 8fh ? unimplemented ? ? 90h vinlvl uvloen ? uvlo5 uvlo4 uvlo3 uvlo2 uvlo1 uvlo0 0-xx xxxx 0-uu uuuu 91h occon ocen ocleb1 ocleb0 ooc4 ooc3 ooc2 ooc1 ooc0 0xxx xxxx 0uuu uuuu 92h ? ? ? reserved reserved reserved reserved reserved reserved --xx xxxx --uu uuuu 93h csgscon ? reserved reserved reserved csgs3 csgs2 csgs1 csgs0 -xxx xxxx -uuu uuuu 94h ? reserved reserved reserved reserv ed reserved reserved reserved reserved xxxx xxxx uuuu uuuu 95h csdgcon csdgen ? ? ? reserved csdg2 csdg1 csdg0 0--- xxxx 0--- uuuu 96h ? ? ? ? ? reserved reserved reserved reserved ---- xxxx ---- uuuu 97h vzccon vzc7 vzc6 vzc5 vzc4 vzc3 vzc2 vzc1 vzc0 xxxx xxxx uuuu uuuu 98h cmpzcon cmpzf3 cmpzf2 cmpzf1 cmpzf0 cmpzg3 cmpzg2 cmpzg1 cmpzg0 xxxx xxxx uuuu uuuu 99h ouvcon ouv7 ouv6 ouv5 ouv4 ouv3 ouv2 ouv1 ouv0 xxxx xxxx uuuu uuuu 9ah oovcon oov7 oov6 oov5 oov4 oov3 oov2 oov1 oov0 xxxx xxxx uuuu uuuu 9bh deadcon hdly3 hdly2 hdly1 hdly0 ldly3 ldly2 ldly1 ldly0 xxxx xxxx uuuu uuuu 9ch slpcrcon slpg3 slpg2 slpg1 slpg0 slps3 slps2 slps1 slps0 xxxx xxxx uuuu uuuu 9dh slvgncon ? ? ? slvgn4 slvgn3 slvgn2 slvgn1 slvgn0 ---x xxxx ---u uuuu 9eh releff msdone re6 re5 re4 re3 re2 re1 re0 0000 0000 0000 0000 9fh ? unimplemented ? ? legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: irp & rp1 bits are reserved, always maintain these bits clear. 3: ra3 pull-up is enabled when pin is configured as mclr in configuration word. 4: mclr and wdt reset does not affect the previous value data latch. the iocf bit will be cleared upon reset but will set again if the mismatch exists. ? 2013 microchip technology inc. ds22331a-page 73 mcp19111 table 11-4: mcp19111 special registers summary bank 2 adr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset value on all other resets (1) bank 2 100h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx xxxx xxxx 101h tmr0 timer0 module?s register xxxx xxxx uuuu uuuu 102h pcl program counter's (pc) least significant byte 0000 0000 0000 0000 103h status irp (2) rp1 (2) rp0 to pd zdcc 0001 1xxx 000q quuu 104h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 105h wpugpa ? ? wpua5 ? wpua3 wpua2 wpua1 wpua0 --1- 1111 --u- uuuu 106h wpugpb wpub7 wpub6 wpub5 wpub4 ? wpub2 wpub1 ? 1111 -11- uuuu -uu- 107h pe1 decon dvrstr hdlyby ldlyby pden puen uvtee ovtee 0000 1100 0000 1100 108h buffcon mltph2 mltph1 mltph0 asel4 asel3 asel2 asel1 asel0 0000 0000 0000 0000 109h abecon ovdcen uvdcen measen slcpby crtmen tmpsen reciren pathen 0000 0000 0000 0000 10ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 10bh intcon gie peie t0ie inte ioce t0if intf iocf (3) 0000 000x 0000 000u 10ch ? unimplemented ? ? 10dh ? unimplemented ? ? 10eh ? unimplemented ? ? 10fh ? unimplemented ? ? 110h sspadd add<7:0> 0000 0000 0000 0000 111h sspbuf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 112h sspcon1 wcol sspov sspen ckp sspm>3:0> 0000 0000 0000 0000 113h sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 114h sspcon3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 115h sspmsk msk<7:0> 1111 1111 1111 1111 116h sspstat smp cke d/a psr/w ua bf ? ? 117h sspadd2 add2<7:0> 0000 0000 0000 0000 118h sspmsk2 msk2<7:0> 1111 1111 1111 1111 119h ? unimplemented ? ? 11ah ? unimplemented ? ? 11bh ? unimplemented ? ? 11ch ? unimplemented ? ? 11dh ? unimplemented ? ? 11eh ? unimplemented ? ? 11fh ? unimplemented ? ? legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: irp & rp1 bits are reserved, always maintain these bits clear. 3: mclr and wdt reset does not affect the previous value data latch. the iocf bit will be cleared upon reset but will set again if the mismatch exists. mcp19111 ds22331a-page 74 ? 2013 microchip technology inc. table 11-5: mcp19111 special registers summary bank 3 addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por reset values on all other resets (1) bank 3 180h indf addressing this location uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 181h option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 1111 1111 1111 1111 182h pcl program counter's (pc) least significant byte 0000 0000 0000 0000 183h status irp (2) rp1 (2) rp0 to pd zdc c 0001 1xxx 000q quuu 184h fsr indirect data memory address pointer xxxx xxxx uuuu uuuu 185h ioca ioca7 ioca6 ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 0000 0000 0000 0000 186h iocb iocb7 iocb6 iocb5 iocb4 ? iocb2 iocb1 iocb0 0000 -000 0000 -000 187h ansela ? ? ? ? ansa3 ansa2 ansa1 ansa0 ---- 1111 ---- 1111 188h anselb ? ? ansb5 ansb4 ? ansb2 ansb1 ? --11 -11- --11 -11- 189h ? unimplemented ? ? 18ah pclath ? ? ? write buffer for upper 5 bits of program counter ---0 0000 ---0 0000 18bh intcon gie peie t0ie inte ioce t0if intf iocf (4) 0000 000x 0000 000u 18ch porticd ( 5 ) in-circuit debug port register 18dh trisicd ( 5 ) in-circuit debug tris register 18eh ickbug ( 5 ) in-circuit debug register 0--- ---- 0--- ---- 18fh bigbug ( 5 ) in-circuit debug breakpoint register ---- ---- ---- ---- 190h pmcon1 ? calsel ? ? ?wrenwr rd -0-- -000 -0-- -000 191h pmcon2 program memory control register 2 (not a physical register) ---- ---- ---- ---- 192h pmadrl pmadrl7 pmadrl6 pmadrl5 pmadrl4 pmadrl3 pmadrl2 pmadrl1 pmadrl0 0000 0000 0000 0000 193h pmadrh ? ? ? ? ? pmadrh2 pmadrh1 pmadrh0 ---- -000 ---- -000 194h pmdatl pmdatl7 pmdatl6 pmdatl5 pmdatl4 pmdatl3 pmdatl2 pmdatl1 pmdatl0 0000 0000 0000 0000 195h pmdath ? ? pmdath5 pmdath4 pmdath3 pmdath2 pmdath1 pmdath0 --00 0000 --00 0000 196h ? unimplemented ? ? 197h ? unimplemented ? ? 198h osccal ? fcalt6 fcalt5 fcalt4 fcalt3 fcalt2 fcalt1 fcalt0 xxxx xxxx uuuu uuuu 199h dovcal ? ? ? ? dovt3 dovt2 dovt1 dovt0 xxxx xxxx uuuu uuuu 19ah ttacal ? ? ? ? tta3 tta2 tta1 tta0 xxxx xxxx uuuu uuuu 19bh bgrcal reserve d reserved reserved reserved bgrt3 bgrt2 bgrt1 bgrt0 xxxx xxxx uuuu uuuu 19ch vrocal ? ? ? ? vrot3 vrot2 vrot1 vrot0 xxxx xxxx uuuu uuuu 19dh zrocal ? ? ? ? zrot3 zrot2 zrot1 zrot0 xxxx xxxx uuuu uuuu 19eh ? unimplemented ? ? 19fh atstcon ? ? ? ? hidis lodis bnchen drvdis 1--0 0001 1--0 0001 legend: ? = unimplemented locations read as ?0?, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. 2: irp & rp1 bits are reserved, always maintain these bits clear. 3: ra3 pull-up is enabled when pin is configured as mclr in configuration word. 4: mclr and wdt reset does not affect the previous value data latch. the iocf bit will be cleared upon reset but will set again if the mismatch exists. 5: only accessible when dbgen = 0 and ickbug ? 2013 microchip technology inc. ds22331a-page 75 mcp19111 11.3.0.1 option register the option register is a readable and writable register, which contains various control bits to configure: ? timer0/wdt prescaler ? external gpa2/int interrupt ?timer0 ? weak pull-ups on portgpa and portgpb note 1: to achieve a 1:1 prescaler assignment for timer0, assign the prescaler to the wdt by setting psa bit to ?1? of the option register. see section 23.1.3 ?software programmable prescaler? register 11-2: option_reg: option register ( note 1 ) r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 rapu intedg t0cs t0se psa ps2 ps1 ps0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 rapu : port gpx pull-up enable bit 1 = port gpx pull-ups are disabled 0 = port gpx pull-ups are enabled bit 6 intedg: interrupt edge select bit 0 = interrupt on rising edge of int pin 1 = interrupt on falling edge of int pin bit 5 t0ce: tmr0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock bit 4 t0se: tmr0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is assigned to wdt 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits note 1: individual wpux bit must also be enabled. bit value tmr0 rate wdt rate 000 1: 2 1: 1 001 1: 4 1: 2 010 1: 8 1: 4 011 1: 16 1: 8 100 1: 32 1: 16 101 1: 64 1: 32 110 1: 128 1: 64 111 1: 256 1: 128 mcp19111 ds22331a-page 76 ? 2013 microchip technology inc. 11.4 pcl and pclath the program counter (pc) is 13 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<12:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 11-2 shows the two situations for loading the pc. the upper example in figure 11-2 shows how the pc is loaded on a write to pcl (pclath<4:0> ? pch). the lower example in figure 11-2 shows how the pc is loaded during a call or goto instruction (pclath<4:3> ? pch). figure 11-2: loading of pc in different situations 11.4.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<12:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire content of the program counter to be changed by writing the desired upper 5 bits to the pclath register. when the lower 8 bits are written to the pcl register, all 13 bits of the program counter will change to the values contained in the pclath register and those being written to the pcl register. 11.4.2 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). care should be exercised when jumping into a look-up table or program branch table (computed goto ) by modifying the pcl register. assuming that pclath is set to the table start address, if the table length is greater than 255 instructions or if the lower 8 bits of the memory address rolls over from 0xffh to 0x00h in the middle of the table, then pclath must be incremented for each address rollover that occurs between the table beginning and the table location within the table. for more information, refer to application note an556 ? ?implementing a table read? (ds00556). 11.4.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. 11.4.4 stack the mcp19111 has an 8-level x 1-bit wide hardware stack (refer to figure 11-1 ). the stack space is not part of either program or data space and the stack pointer is not readable or writable. the pc is pushed onto the stack when call instruction is executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer. this means that after the stack has been pushed eight times, the ninth push overwrites the value that was stored from the first push. the tenth push overwrites the second push (and so on). 11.5 indirect addressing, indf and fsr registers the indf register is not a physical register. addressing the indf register will cause indirect addressing. indirect addressing is possible by using the indf register. any instruction using the indf register actually accesses data pointed to by the file select register (fsr). reading indf itself indirectly will produce 00h. writing to the indf register directly results in a no operation (although status bits may be affected). an effective 9-bit address is obtained by concatenating the 8-bit fsr and the irp bit of the status register, as shown in figure 11-3 . a simple program to clear ram location 40h-7fh using indirect addressing is shown in example 11-3 . pc 12 8 7 0 5 pclath<4:0> pclath instruction with alu result goto , call opcode <10:0> 8 pc 12 11 10 0 11 pclath<4:3> pch pcl 87 2 pclath pch pcl destination note 1: there are no status bits to indicate stack overflow or stack underflow conditions. 2: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call , return , retlw and retfie instructions or the vectoring to an interrupt address. ? 2013 microchip technology inc. ds22331a-page 77 mcp19111 example 11-3: indirect addressing figure 11-3: direct/indirect addressing movlw 0x40 ;initialize pointer movwf fsr ;to ram next clrf indf ;clear indf register incf fsr ;inc pointer btfss fsr,7 ;all done? goto next ;no clear next continue ;yes continue data memory indirect addressing direct addressing bank select location select rp1 rp0 6 0 from opcode irp file select register 7 0 bank select location select 00 01 10 11 180h 1ffh 00h 7fh bank 0 bank 1 bank 2 bank 3 for memory map detail, see figure 11-2 . mcp19111 ds22331a-page 78 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 79 mcp19111 12.0 device configuration device configuration consists of configuration word, code protection and device id. 12.1 configuration word there are several configuration word bits that allow different timers to be enabled and memory protection options. these are implemented as configuration word at 2007h . note: the d bgen bit in configuration word is managed automatically by device development tools, including debuggers and programmers. for normal device operation, this bit should be maintained as a ' 1 '. register 12-1: config ? co nfiguration word register r/p-1 u-1 r/p-1 r/p-1 u-1 u-1 dbgen ?wrt1wrt0 ? ? bit 13 bit 8 u-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 u-1 u-1 ?cp mclre pwrte wdte ? ? ? bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13 dbgen : icd debug bit 1 = icd debug mode disabled 0 = icd debug mode enabled bit 12 unimplemented: read as ? 1 ? bit 11-10 wrt<1:0>: flash program memory self write enable bit 11 = write protection off 10 = 000h to 3ffh write protected, 400h to fffh may be modified by pmcon1 control 01 = 000h to 7ffh write protected, 800h to fffh may be modified by pmcon1 control 00 = 000h to fffh write protected, entire program memory is write protected. bit 9-7 unimplemented: read as ? 1 ? bit 6 cp : code protection 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 5 mclre : mclr pin function select 1 =mclr pin is mclr function and weak internal pull-up is enabled 0 =mclr pin is alternate function, mclr function is internally disabled bit 4 pwrte : power-up timer enable bit ( 1 ) 1 = pwrt disabled 0 = pwrt enabled bit 3 wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 2-0 unimplemented: read as ? 1 ? note 1: bit is reserved and not controlled by user. mcp19111 ds22331a-page 80 ? 2013 microchip technology inc. 12.2 code protection code protection allows the device to be protected from unauthorized access. internal access to the program memory is unaffected by any code protection setting. 12.2.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in the configuration word. when cp = 0 , external reads and writes of the program memory are inhibited and a read will return all ? 0 ?s. the cpu can continue to read program memory, regardless of the protection bit settings. writing the program memory is dependent upon the write protection setting. see section 12.3 ?write protection? for more information. 12.3 write protection write protection allows the device to be protected from unintended self-writes. applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in the configuration word define the size of the program memory block that is protected. 12.4 id locations four memory locations (2000h ? 2003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are not accessible during normal execution but are readable and writable during program/verify mode. only the least significant 7 bits of the id locations are reported when using mplab integrated development environment (ide). 12.5 device id and revision id the memory location 2006h is where the device id and revision id are stored. the upper nine bits hold the device id. the lower five bits hold the revision id. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. register 12-2: deviceid: device id register ( 1 ) rrr r r r dev<8:3> bit 13 bit 8 rrrrrrrr dev<2:0> rev<4:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 13-5 dev<8:0> : device id bits bit 4-0 rev<4:0>: revision id bits these bits are used to identify the revision. note 1: this location cannot be written. device deviceid<13:0> values dev<8:0> rev<4:0> mcp19111 10 1111 100 x xxxx ? 2013 microchip technology inc. ds22331a-page 81 mcp19111 13.0 oscillator modes the mcp19111 has one oscillator configuration which is an 8 mhz internal oscillator. 13.1 internal oscillator (intosc) the internal oscillator module provides a system clock source of 8 mhz. the frequency of the internal oscillator can be trimmed with a calibration value in the osctune register. 13.2 oscillator calibration the 8 mhz internal oscillator is factory calibrated. the factory calibration values reside in the read-only calibration word 1 register. these values must be read from the calibration word 1 register and stored in the osccal register. refer to section 18.0 ?flash program memory control? for the procedure on reading from program memory. 13.3 frequency tuning in user mode in addition to the factory calibration, the base frequency can be tuned in the user's application. this frequency tuning capability allows the user to deviate from the factory calibrated frequency. the user can tune the frequency by writing to the osctune register (see register 13-1 ). note 1: the fcal<6:0> bits from the calibration word 1 register must be written into the osccal register to calibrate the internal oscillator. register 13-1: osctune ? oscillator tuning register u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? tun4 tun3 tun2 tun1 tun0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-5 unimplemented: read as ? 0 ? bit 4-0 tun<4:0>: frequency tuning bits 01111 = maximum frequency 01110 = ? ? ? 00001 = 00000 = center frequency. oscillator module is running at the calibrated frequency. 11111 = ? ? ? 10000 = minimum frequency mcp19111 ds22331a-page 82 ? 2013 microchip technology inc. 13.3.1 oscillator delay upon power-up, wake-up and base frequency change in applications where the osctune register is used to shift the frequency of the internal oscillator, the application should not expect the frequency of the internal oscillator to stabilize immediately. in this case, the frequency may shift gradually toward the new value. the time for this frequency shift is less than eight cycles of the base frequency. on power up, the device is held in reset by the power-up time, if the power-up timer is enabled. following a wake-up from sleep mode or por, an internal delay of ~10 s is invoked to allow the memory bias to stabilize before program execution can begin. table 13-1: summary of registers associated with clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osctune ? ? ? tun4 tun3 tun2 tun1 tun0 81 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by clock sources. table 13-2: summary of calibration word associated with clock sources name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page calwd1 13:8 ? ? ? ? dov3 dov2 dov1 dov0 57 7:0 ? fcal6 fcal5 fcal4 fcal3 fcal2 fcal1 fcal0 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by clock sources. ? 2013 microchip technology inc. ds22331a-page 83 mcp19111 14.0 resets the reset logic is used to place the mcp19111 into a known state. the source of the reset can be determined by using the device status bits. there are multiple ways to reset this device: ? power-on reset (por) ? overtemperature reset (ot) ?mclr reset ?wdt reset to a l l o w v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a por event. some registers are not affected in any reset condition; their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?reset state? on: ? power-on reset ?mclr reset ?mclr reset during sleep ? wdt reset wdt wake-up does not cause register resets in the same manner as a wdt reset since wake-up is viewed as the resumption of normal operation. to and pd bits are set or cleared differently in different reset situations, as indicated in tab l e 1 4- 1 . software can use these bits to determine the nature of the reset. see table 14-2 for a full description of reset states of all registers. a simplified block diagram of the on-chip reset circuit is shown in figure 14-1 . the mclr reset path has a noise filter to detect and ignore small pulses. see section 5.0 ?digital electrical characteristics? for pulse-width specifications. figure 14-1: simplified block di agram of on-chip reset circuit s r q external reset mclr /v pp pin v dd wdt module v dd rise detect on-chip wdt time-out power-on reset pwrt chip_reset 11-bit ripple counter reset enable pwrt sleep note 1: refer to the configuration word register ( register 12-1 ). rc osc table 14-1: time-out in various situations power-up wake-up from sleep pwrte = 0 pwrte = 1 t pwrt ?? mcp19111 ds22331a-page 84 ? 2013 microchip technology inc. 14.1 power-on reset (por) the on-chip por circuit holds the chip in reset until v dd has reached a high enough level for proper operation. to take advantage of the por, simply connect the mclr pin through a resistor to v dd . this will eliminate external rc components usually needed to create power-on reset. when the device starts normal operation (exits the reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must be met to ensure proper operation. if these conditions are not met, the device must be held in reset until the operating conditions are met. 14.2 mclr mcp19111 has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. it should be noted that a wdt reset does not drive mclr pin low. voltages applied to the mclr pin that exceed its specification can result in both mclr resets and excessive current beyond the device specification during the esd event. for this reason, microchip recommends that the mclr pin no longer be tied directly to v dd . the use of an rc network, as shown in figure 14-2 , is suggested. an internal mclr option is enabled by clearing the mclre bit in the configuration word register. when mclre = 0 , the reset signal to the chip is generated internally. when the mclre = 1 , the mclr pin becomes an external reset input. in this mode, the mclr pin has a weak pull-up to v dd . figure 14-2: recommended mclr circuit table 14-2: status/pcon bits and their significance por to pd condition 011 power-on reset u0u wdt reset u00 wdt wake-up uuu mclr reset during normal operation u10 mclr reset during sleep legend: u = unchanged, x = unknown note: the por circuit does not produce an internal reset when v dd declines. to re-enable the por, v dd must reach v ss for a minimum of 100 s. v dd mclr r 1 1k ? (or greater) c 1 0.1 f (optional, not critical) r2 100 ? (needed with sw1 (optional) mcp19111 capacitor) ? 2013 microchip technology inc. ds22331a-page 85 mcp19111 14.3 power-up timer (pwrt) the power-up timer provides a fixed 64 ms (nominal) time-out on power-up only, from por reset. the power-up timer operates from an internal rc oscillator. the chip is kept in reset as long as pwrt is active. the pwrt delay allows the v dd to rise to an acceptable level. a configuration bit (p wrte ), can disable (if set) or enable (if cleared or programmed) the power-up timer. the power-up timer delay will vary from chip-to-chip due to: ?v dd variation ? temperature variation ? process variation 14.4 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register are changed to indicate the wdt reset. see section 17.0 ?watchdog timer (wdt)? for more information. 14.5 power-up timer the power-up timer optionally delays device execution after a por event. this timer is typically used to allow v dd to stabilize before allowing the device to start running. the power-up timer is controlled by the pwrte bit of configuration word. 14.6 start-up sequence upon the release of a por, the following must occur before the device will begin executing: ? power-up timer runs to completion (if enabled) ? oscillator start-up timer runs to completion ?mclr must be released (if enabled) the total time-out will vary based on pwrte bit status. for example, with pwrte bit erased (pwrt disabled), there will be no time-out at all. figures 14-3 , 14-4 and 14-5 depict time-out sequences. since the time-outs occur from the por pulse, if mclr is kept low long enough, the time-outs will expire. then, bringing mclr high will begin execution immediately (see figure 14-4 ). this is useful for testing purposes or to synchronize more than one mcp19111 device operating in parallel. 14.6.1 power co ntrol (pcon) register the power control register pcon (address 8eh) has two status bits to indicate what type of reset occurred last. figure 14-3: time-out sequence on power-up (delayed mclr ): case 1 note: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resis- tor of 50-100 ? should be used when applying a ?low? level to the mclr pin, rather than pulling this pin directly to v ss . t pwrt t ioscst v dd mclr internal por pwrt time-out ost time-out internal reset mcp19111 ds22331a-page 86 ? 2013 microchip technology inc. figure 14-4: time-out sequence on power-up (delayed mclr ): case 2 figure 14-5: time-out sequ ence on power-up (mclr with v dd ) v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ioscst v dd mclr internal por pwrt time-out ost time-out internal reset t pwrt t ioscst ? 2013 microchip technology inc. ds22331a-page 87 mcp19111 table 14-3: initialization condition for registers register address power-on reset mclr reset wdt reset wake-up from sleep through interrupt wake-up from sleep through wdt time-out w? xxxx xxxx uuuu uuuu uuuu uuuu indf 00h/80h/ 100h/180h xxxx xxxx xxxx xxxx uuuu uuuu tmr0 01h/101h xxxx xxxx uuuu uuuu uuuu uuuu pcl 02h/82h/ 102h/182h 0000 0000 0000 0000 pc + 1 ( 3 ) status 03h/83h/ 103h/183h 0001 1xxx 000q quuu ( 4 ) uuuq quuu ( 4 ) fsr 04h/84h/ 104h/184h xxxx xxxx uuuu uuuu uuuu uuuu portgpa 05h xxxx xxxx uuuu uuuu uuuu uuuu portgpb 06h xxx- xxxx uuu- uuuu uuu- uuuu pir1 07h -000 --00 -000 --00 -uuu --uu pir2 08h 0-00 --00 0-00 --00 u-uu --uu pcon 09h ---- -qq- ---- -uu- ---- -uu- pclath 0ah/8ah/ 10ah/18ah ---0 0000 ---0 0000 ---u uuuu intcon 0bh/8bh/ 10bh/18bh 0000 000x 0000 000u uuuu uuuu ( 2 ) tmr1l 0ch xxxx xxxx uuuu uuuu uuuu uuuu tmr1h 0dh xxxx xxxx uuuu uuuu uuuu uuuu t1con 0eh --00 --00 --uu --uu --uu --uu tmr2 0fh 0000 0000 uuuu uuuu uuuu uuuu t2con 10h ---- -000 ---- -000 ---- -uuu pr2 11h 1111 1111 1111 1111 uuuu uuuu pwmphl 13h xxxx xxxx uuuu uuuu uuuu uuuu pwmphh 14h xxxx xxxx uuuu uuuu uuuu uuuu pwmrl 15h xxxx xxxx uuuu uuuu uuuu uuuu pwmrh 16h xxxx xxxx uuuu uuuu uuuu uuuu ovccon 19h 0000 0000 0000 0000 uuuu uuuu ovfcon 1ah 0--0 0000 0--0 0000 u--u uuuu osctune 1bh ---0 0000 ---0 0000 ---u uuuu adresl ( 1 ) 1ch xxxx xxxx uuuu uuuu uuuu uuuu adresh ( 1 ) 1dh ---- --xx ---- --uu ---- ---uu adcon0 ( 1 ) 1eh -000 0000 -000 0000 -uuu uuuu adcon1 ( 1 ) 1fh -000 ---- -000 ---- -uuu ---- option_reg 81h/181h 1111 1111 1111 1111 uuuu uuuu TRISGPA 85h 1111 1111 1111 1111 uuuu uuuu trisgpb 86h 1111 1111 1111 1111 uuuu uuuu legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pirx will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 14-5 for reset value for specific condition. mcp19111 ds22331a-page 88 ? 2013 microchip technology inc. pie1 87h -000 --00 -000 --00 -uuu --uu pie2 88h 0-00 --00 0-00 --00 u-uu --uu apfcon 89h ---- ---0 ---- ---0 ---- ---u vinlvl 90h 0-xx xxxx 0-uu uuuu u-uu uuuu occon 91h 0xxx xxxx 0uuu uuuu uuuu uuuu csgscon 93h -xxx xxxx -uuu uuuu -uuu uuuu csdgcon 95h 0--- xxxx 0--- uuuu u--- uuuu vzccon 97h xxxx xxxx uuuu uuuu uuuu uuuu cmpzcon 98h xxxx xxxx uuuu uuuu uuuu uuuu ouvcon 99h xxxx xxxx uuuu uuuu uuuu uuuu oovcon 9ah xxxx xxxx uuuu uuuu uuuu uuuu deadcon 9bh xxxx xxxx uuuu uuuu uuuu uuuu slpcrcon 9ch xxxx xxxx uuuu uuuu uuuu uuuu slvgncon 9dh ---x xxxx ---u uuuu ---u uuuu releff 9eh 0000 0000 0000 0000 uuuu uuuu wpugpa 105h --1- 1111 --u- uuuu --u- uuuu wpugpb 106h 1111 -11- uuuu -uu- uuuu -uu- pe1 107h 0000 1100 0000 1100 uuuu uuuu buffcon 108h 000- 0000 000- 0000 uuu- uuuu abecon 109h 0000 0000 0000 0000 uuuu uuuu sspadd 110h 0000 0000 0000 0000 uuuu uuuu sspbuf 111h xxxx xxxx uuuu uuuu uuuu uuuu sspcon1 112h 0000 0000 0000 0000 uuuu uuuu sspcon2 113h 0000 0000 0000 0000 uuuu uuuu sspcon3 114h 0000 0000 0000 0000 uuuu uuuu sspmsk 115h 1111 1111 1111 1111 uuuu uuuu sspstat 116h sspadd2 117h 0000 0000 0000 0000 uuuu uuuu sspmsk2 118h 1111 1111 1111 1111 uuuu uuuu ioca 185h 0000 0000 0000 0000 uuuu uuuu iocb 186h 0000 -000 0000 -000 uuuu -uuu ansela 187h ---- 1111 ---- 1111 ---- uuuu anselb 188h --11 -11- --11 -11- --uu -uu- pmcon1 190h -0-- -000 -0-- -000 -u-- -uuu pmcon2 191h ---- ---- ---- ---- ---- ---- pmadrl 192h 0000 0000 0000 0000 uuuu uuuu pmadrh 193h ---- -000 ---- -000 ---- -uuu pmdatl 194h 0000 0000 0000 0000 uuuu uuuu table 14-3: initialization conditi on for registers (continued) register address power-on reset mclr reset wdt reset wake-up from sleep through interrupt wake-up from sleep through wdt time-out (continued) legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pirx will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 14-5 for reset value for specific condition. ? 2013 microchip technology inc. ds22331a-page 89 mcp19111 14.7 determining the cause of a reset upon any reset, multiple bits in the status and pcon register are updated to indicate the cause of the reset. ta b l e 1 4 - 4 and tab l e 1 4- 5 show the reset conditions of these registers. pmdath 195h --00 0000 --00 0000 --uu uuuu osccal 198h -xxx xxxx -uuu uuuu -uuu uuuu dovcal 199h ---- xxxx ---- uuuu ---- uuuu ttacal 19ah ---- xxxx ---- uuuu ---- uuuu bgrcal 19bh ---- xxxx ---- uuuu ---- uuuu vrocal 19ch ---- xxxx ---- uuuu ---- uuuu zrocal 19dh ---- xxxx ---- uuuu ---- uuuu atstcon 19f 1--- 0001 1--- 0001 u--- uuuu table 14-3: initialization conditi on for registers (continued) register address power-on reset mclr reset wdt reset wake-up from sleep through interrupt wake-up from sleep through wdt time-out (continued) legend: u = unchanged, x = unknown, ? = unimplemented bit, reads as ? 0 ?, q = value depends on condition. note 1: if v dd goes too low, power-on reset will be activated and registers will be affected differently. 2: one or more bits in intcon and/or pirx will be affected (to cause wake-up). 3: when the wake-up is due to an interrupt and the gie bit is set, the pc is loaded with the interrupt vector (0004h). 4: see table 14-5 for reset value for specific condition. table 14-4: reset status bits and their significance por to pd condition 011 power-on reset u0u wdt reset u00 wdt wake-up from sleep u10 interrupt wake-up from sleep uuu mclr reset during normal operation u10 mclr reset during sleep 00x not allowed. to is set on por 0x0 not allowed. pd is set on por table 14-5: reset condition for special registers ( note 2 ) condition program counter status register pcon register power-on reset 0000h 0001 1xxx ---- -u0- mclr reset during normal operation 0000h 000u uuuu ---- -uu- mclr reset during sleep 0000h 0001 0uuu ---- -uu- wdt reset 0000h 0000 uuuu ---- -uu- wdt wake-up from sleep pc + 1 uuu0 0uuu ---- -uu- interrupt wake-up from sleep pc + 1 ( 1 ) uuu1 0uuu ---- -uu- legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1. 2: if a status bit is not implemented, that bit will be read as ? 0 ?. mcp19111 ds22331a-page 90 ? 2013 microchip technology inc. 14.8 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: ? power-on reset (por ) ? over temperature (ot ) the pcon register bits are shown in register 14-1 . register 14-1: pcon ? power control register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 u-0 ? ? ? ? ?ot por ? bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as ' 0 ' bit 2 ot : overtemperature reset status bit 1 = no overtemperature reset occurred 0 = an overtemperature reset occurred (must be set in software after an overtemperature occurs) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 unimplemented: read as ' 0 ' table 0-1: summary of registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page pcon ? ? ? ? ?ot por ? 90 status ipr rp1 rp0 to pd zdcc 69 legend: ? = unimplemented bit, reads as ? 0 ?. shaded cells are not used by resets. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. ? 2013 microchip technology inc. ds22331a-page 91 mcp19111 15.0 interrupts the mcp19111 has multiple sources of interrupt: ? external interrupt (int pin) ? interrupt-on-change (ioc) interrupts ? timer0 overflow interrupt ? timer1 overflow interrupt ? timer2 match interrupt ? adc interrupt ? system overvoltage error ? system under voltage error ? system overcurrent error ? ssp ?bcl ? system input under voltage error the interrupt control register (intcon) and peripheral interrupt request registers (pirx) record individual interrupt requests in flag bits. the intcon register also has individual and global interrupt enable bits. the global interrupt enable bit, gie of the intcon register, enables (if set) all unmasked interrupts, or disables (if cleared) all interrupts. individual interrupts can be disabled through their corresponding enable bits in the intcon register and piex registers. gie is cleared on reset. when an interrupt is serviced, the following actions occur automatically: ? the gie is cleared to disable any further interrupt. ? the return address is pushed onto the stack. ? the pc is loaded with 0004h. the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr, to avoid repeated interrupts. because the gei bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exists the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupt?s oper- ation, refer to its peripheral chapter. 15.1 interrupt latency for external interrupt events, such as the int pin or portgpx change interrupt, the interrupt latency will be three or four instruction cycles. the exact latency depends upon when the interrupt event occurs (see figure 15-2 ). the latency is the same for one or two-cycle instructions. 15.2 gpa2/int interrupt the external interrupt on the gpa2/int pin is edge-triggered; either on the rising edge, if the intedg bit of the option register is set, or the falling edge, if the intedg bit is cleared. when a valid edge appears on the gpa2/int pin, the intf bit of the intcon register is set. this interrupt can be disabled by clearing the inte control bit of the intcon register. the intf bit must be cleared by software in the interrupt service routine before re-enabling this interrupt. the gpa2/int interrupt can wake-up the processor from sleep, if the inte bit was set prior to going into sleep. see section 16.0 ?power-down mode (sleep)? for details on sleep, and section 16.1 ?wake-up from sleep? for timing of wake-up from sleep through gpa2/int interrupt. note 1: individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the gie bit. 2: when an instruction that clears the gie bit is executed, any interrupts that were pending for execution in the next cycle are ignored. the interrupts, which were ignored, are still pending to be serviced when the gie bit is set again. note: the ansel register must be initialized to configure an analog channel as a digital input. pins configured as analog inputs will read ? 0 ? and cannot generate an interrupt. mcp19111 ds22331a-page 92 ? 2013 microchip technology inc. figure 15-1: interrupt logic figure 15-2: int pin interrupt timing tmr1if tmr1ie sspif sspie t0if t0ie intf inte gie peie wake-up (if in sleep mode) interrupt to cpu peif adif adie uvif uvie ovif ovie ocif ocie vinif vinie bclif bclie tmr2if tmr2ie iocf ioce q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 clkin clkout int pin intf flag (intcon reg.) gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-4 t cy . synchronous latency = 3 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout is available only in intosc and rc oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 5.0 ?digital electrical characteristics? . 5: intf is enabled to be set any time during the q4-q1 cycles. ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 1 ) ? 2013 microchip technology inc. ds22331a-page 93 mcp19111 15.3 interrupt control registers 15.3.1 intcon register the intcon register is a readable and writable regis- ter, that contains the various enable and flag bits for the tmr0 register overflow, interrupt-on-change and exter- nal int pin interrupts. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. register 15-1: intcon ? interrupt control register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-x gie peie t0ie inte ioce t0if intf iocf bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gie: global interrupt enable bit 1 = enables all unmasked interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all unmasked peripheral interrupts 0 = disables all peripheral interrupts bit 5 t0ie: tmr0 overflow interrupt enable bit 1 = enables the tmr0 interrupt 0 = disables the tmr0 interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 ioce: interrupt-on-change enable bit ( 1 ) 1 = enables the interrupt-on-change 0 = disables the interrupt-on-change bit 2 t0if: tmr0 overflow interrupt flag bit ( 2 ) 1 = tmr0 register has overflowed (must be cleared in software) 0 = tmr0 register did not overflow bit 1 intf: external interrupt flag bit 1 = the external interrupt occurred (must be cleared in software) 0 = the external interrupt did not occur bit 0 iocf: interrupt-on-change interrupt flag bit 1 = when at least one of the interrupt-on-change pins changed state 0 = none of the interrupt-on-change pins have changed state note 1: ioc register must also be enabled. 2: t0if bit is set when tmr0 rolls over. tmr0 is unchanged on reset and should be initialized before clear- ing t0if bit. mcp19111 ds22331a-page 94 ? 2013 microchip technology inc. 15.3.1.1 pie1 register the pie1 register contains the peripheral interrupt enable bits, as shown in register 15-2 . note 1: bit peie of the intcon register must be set to enable any peripheral interrupt. register 15-2: pie1 ? peripheral interrupt enable register 1 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ? adie bclie sspie ? ? tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ' 0 ' bit 6-0 adie: adc interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 6-0 bclie: mssp bus collision interrupt enable bit 1 = enables the mssp bus collision interrupt 0 = disables the mssp bus collision interrupt bit 6-0 sspie: synchronous serial port (mssp) interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 6-0 unimplemented: read as 0 bit 6-0 tmr2ie: timer2 interrupt enable 1 = enables the timer2 interrupt 0 = disables the timer2 interrupt bit 6-0 tmr1ie: timer1 interrupt enable 1 = enables the timer1 interrupt 0 = disables the timer1 interrupt ? 2013 microchip technology inc. ds22331a-page 95 mcp19111 15.3.1.2 pie2 register the pie2 register contains the peripheral interrupt enable bits, as shown in register 15-3 . note 1: bit peie of the intcon register must be set to enable any peripheral interrupt. register 15-3: pie2 ? peripheral interrupt enable register 2 u-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 uvie ?ocieovie ? ? vinie ? bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 uvie: output under voltage interrupt enable bit 1 = enables the uv interrupt 0 = disables the uv interrupt bit 6 unimplemented: read as ' 0 ' bit 5 ocie: output overcurrent interrupt enable bit 1 = enables the oc interrupt 0 = disables the oc interrupt bit 4 ovie: output overvoltage interrupt enable bit 1 = enables the ov interrupt 0 = disables the ov interrupt bit 3-2 unimplemented: read as ' 0 ' bit 1 vinie: v in uvlo interrupt enable 1 = enables the v in uvlo interrupt 0 = disables the v in uvlo interrupt bit 0 unimplemented: read as ' 0 ' mcp19111 ds22331a-page 96 ? 2013 microchip technology inc. 15.3.1.3 pir1 register the pir1 register contains the peripheral interrupt flag bits, as shown in register 15-4 . note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 15-4: pir1 ? periphe ral interrupt flag register 1 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 r/w-0 r/w-0 ? adif bclif sspif ? ? tmr2if tmr1if bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ' 0 ' bit 6 adif: adc interrupt flag bit 1 = adc conversion complete 0 = adc conversion has not completed or has not been started bit 5 bclif: mssp bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 sspif: synchronous serial port (mssp) interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3-2 unimplemented: read as ' 0 ' bit 1 tmr2if: timer2 to pr2 match interrupt flag 1 = timer2 to pr2 match occurred (must be cleared in software) 0 = timer2 to pr2 match did not occur bit 0 tmr1if: timer1 interrupt flag 1 = timer1 rolled over (must be cleared in software) 0 = timer1 has not rolled over ? 2013 microchip technology inc. ds22331a-page 97 mcp19111 15.3.1.4 pir2 register the pir2 register contains the peripheral interrupt flag bits, as shown in register 15-5 . note 1: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 15-5: pir2 ? peripheral interrupt flag register 2 r/w-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0 u-0 uvif ?ocifovif ? ?vinif ? bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 uvif: output undervoltage error interrupt flag bit 1 = output undervoltage error has occurred 0 = output undervoltage error has not occurred bit 6 unimplemented: read as ' 0 ' bit 5 ocif: output overcurrent error interrupt flag bit 1 = output overcurrent error has occurred 0 = output overcurrent error has not occurred bit 4 ovif: output overvoltage error interrupt flag bit 1 = output overvoltage error has occurred 0 = output overvoltage error has not occurred bit 3-2 unimplemented: read as ' 0 ' bit 1 vinif: v in status bit 1 = v in is below acceptable level 0 = v in is at acceptable level bit 0 unimplemented: read as ' 0 ' table 15-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie t0ie inte ioce t0if intf iocf 93 option_reg rapu intedg t0ce t0se psa ps2 ps1 ps0 75 pie1 ? adie bclie sspie ? ? tmr2ie tmr1ie 94 pie2 uvie ?ocieovie ? ? vinie ? 95 pir1 ? adif bclif sspif ? ? tmr2if tmr1if 96 pir2 uvif ?ocifovif ? ? vinif ? 97 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by interrupts. mcp19111 ds22331a-page 98 ? 2013 microchip technology inc. 15.4 context saving during interrupts during an interrupt, only the return pc value is saved on the stack. typically, users may wish to save key registers during an interrupt (e.g., w and status registers). this must be implemented in software. temporary holding registers w_temp and status_temp should be placed in the last 16 bytes of gpr (see figure 11-2 ). these 16 locations are common to all banks and do not require banking. this makes context save and restore operations simpler. the code shown in example 15-1 can be used to: ? store the w register ? store the status register ? execute the isr code ? restore the status (and bank select bit register) ? restore the w register example 15-1: saving status and w registers in ram note: the mcp19111 device does not require saving the pclath. however, if computed goto s are used in both the isr and the main code, the pclath must be saved and restored in the isr. movwf w_temp ;copy w to temp register swapf status,w ;swap status to be saved into w ;swaps are used because they do not affect the status bits movwf status_temp ;save status to bank zero status_temp register : :(isr) ;insert user code here : swapf status_temp,w ;swap status_temp register into w ;(sets bank to original state) movwf status ;move w into status register swapf w_temp,f ;swap w_temp swapf w_temp,w ;swap w_temp into w ? 2013 microchip technology inc. ds22331a-page 99 mcp19111 16.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled for operation during sleep. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is not disabled. 5. timer1 oscillator is unaffected, and peripherals that operate from it may continue operation in sleep. 6. adc is unaffected. 7. i/o ports maintain the status they had before sleep was executed (driving high, low or high-impedance). 8. resets other than wdt are not affected by sleep mode. 9. analog circuitry is unaffected by execution of sleep instruction. refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following conditions should be considered: ? i/o pins should not be floating ? external circuitry sinking current from i/o pins ? internal circuitry sourcing current from i/o pins ? current draw from pins with internal weak pull-ups ? modules using timer1 oscillator i/o pins that are high-impedance inputs should be pulled to v dd or gnd externally to avoid switching currents caused by floating inputs. the sleep instruction does not affect the analog circuitry. the enable state of the analog circuitry does not change with the execution of the sleep instruction. examples of internal circuitry that might be sourcing current include modules, such as the dac. see section 22.0 ?analog-to-digital converter (adc) module? for more information on this module. 16.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. por reset 3. watchdog timer, if enabled 4. any external interrupt 5. interrupts by peripherals capable of running during sleep (see individual peripheral for more information) the first two events will cause a device reset. the last three events are considered a continuation of program execution. to determine whether a device reset or wake-up event occurred, refer to section 14.7 ?deter- mining the cause of a reset? . the following peripheral interrupts can wake the device from sleep: 1. timer1 interrupt. timer1 must be operating as an asynchronous counter 2. a/d conversion 3. interrupt-on-change 4. external interrupt from int pin when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will then call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have an nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. mcp19111 ds22331a-page 100 ? 2013 microchip technology inc. 16.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction: - sleep instruction will execute as an nop - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared ? if the interrupt occurs during or after the execution of a sleep instruction: - sleep instruction will be completely executed - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as an nop . figure 16-1: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency ( 1 ) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) dummy cycle pc + 2 0004h 0005h dummy cycle t ost pc + 2 note 1: gie = 1 assumed. in this case, after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line. table 16-1: summary of registers associated with power-down mode name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie t0ie inte ioce t0if intf iocf 93 ioca ioca7 ioca6 ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 120 iocb iocb7 iocb6 iocb5 iocb4 ? iocb2 iocb1 iocb0 120 pie1 ? adie bclie sspie ? ? tmr2ie tmr1ie 94 pie2 uvie ?ocieovie ? ?vinie ? 95 pir1 ? adif bclif sspif ? ? tmr2if tmr1if 96 pir2 uvif ?ocifovif ? ? vinif ? 97 status irp rp1 rp0 to pd zdcc 69 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used in power-down mode. ? 2013 microchip technology inc. ds22331a-page 101 mcp19111 17.0 watchdog timer (wdt) the watchdog timer is a free running timer. the wdt is enabled by setting the wdte bit of the configuration word (default setting). during normal operation, a wdt time-out generates a device reset. if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation. the wdt can be permanently disabled by clearing the wdte bit of the configuration bit. see section 12.1 ?configuration word? for more information. 17.1 watchdog timer (wdt) operation during normal operation, a wdt time-out generates a device reset. if the device is in sleep mode, a wdt time-out causes the device to wake-up and continue with normal operation; this is known as a wdt wake- up. the wdt can be permanently disabled by clearing the wdte configuration bit. the postscaler assignment is fully under software control and can be changed during program execution. 17.2 wdt period the wdt has a nominal time-out period of 18 ms (with no prescaler). the time-out periods vary with temperature, v dd and process variations from part to part (see table 5-4 ). if longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt under software control by writing to the option register. thus, time-out periods up to 2.3 seconds can be realized. the clrwdt and sleep instructions clear the wdt and the prescaler, if assigned to the wdt, and prevent it from timing out and generating a device reset. the to bit in the status register will be cleared upon a watchdog timer time-out. 17.3 wdt programming considerations under worst-case conditions (i.e., v dd = minimum, temperature = maximum, maximum wdt prescaler), it may take several seconds before a wdt time-out occurs. figure 17-1: watchdog timer with shared prescaler block diagram t0cki t0se pin tmr0 watchdog timer wdt time-out ps<2:0> data bus set flag bit t0if on overflow t0cs note 1: t0se, t0cs, psa, ps<2:0> are bits in the option_reg register. 2: wdte bit is in the configuration word register. 0 1 0 1 0 1 8 8 8-bit prescaler 0 1 f osc /4 psa psa psa sync 2 t cy wdte mcp19111 ds22331a-page 102 ? 2013 microchip technology inc. table 17-1: wdt status conditions wdt wdte = 0 cleared clrwdt command exit sleep table 17-2: summary of registers associated with watchdog timer name bit 7bit 6bit 5bit 4bit 3bit 2bit 1bit 0 register on page option_reg rapu intedg t0cs t0se psa ps<2:0> 75 legend: shaded cells are not used by the watchdog timer. note 1: see register 12-1 for operation of all configuration word register bits. table 17-3: summary of co nfiguration word as sociated with watchdog timer name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config 13:8 ? ? d b gen ? wrt1 wrt0 ? ? 79 7:0 ? cp mclre pwrte wdte ? ? ? legend: ? = unimplemented location, read as ? 1 ?. shaded cells are not used by watchdog timer. ? 2013 microchip technology inc. ds22331a-page 103 mcp19111 18.0 flash program memory control the flash program memory is readable and writable during normal operation (full v in range). this memory is not directly mapped in the register file space. instead, it is indirectly addressed through the special function registers (see registers 18-1 to 18-5 ). there are six sfrs used to read and write this memory: ?pmcon1 ?pmcon2 ?pmdatl ?pmdath ? pmadrl ? pmadrh when interfacing the program memory block, the pmdatl and pmdath registers form a two-byte word, which holds the 14-bit data for read/write, and the pmadrl and pmadrh registers form a two-byte word, which holds the 13-bit address of the flash location being accessed. these devices have 4k words of program flash with an address range from 0000h to 0fffh. the program memory allows single word read and a by four word write. a four word write automatically erases the row of the location and writes the new data (erase before write). the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump rated to operate over the voltage range of the device for byte or word operations. when the device is code protected, the cpu may continue to read and write the flash program memory. depending on the settings of the flash program memory enable (wrt<1:0>) bits, the device may or may not be able to write certain blocks of the program memory, however, reads of the program memory are allowed. when the flash program memory code protection (cp ) bit is enabled, the program memory is code protected, and the device programmer (icsp) cannot access data or program memory. 18.1 pmadrh and pmadrl registers the pmadrh and pmadrl registers can address up to a maximum of 4k words of program memory. when selecting a program address value, the most significant byte (msb) of the address is written to the pmadrh register and the least significant byte (lsb) is written to the pmadrl register. 18.2 pmcon1 and pmcon2 registers pmcon1 is the control register for the data program memory accesses. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set in software. they are cleared in hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental premature termination of a write operation. the wren bit, when set, will allow a write operation. on power-up, the wren bit is clear. the calsel bit allows the user to read locations in test memory in case there are calibration bits stored in the calibration word locations that need to be transferred to sfr trim registers. the calsel bit is only for reads, and if a write operation is attempted with calsel = 1 , no write will occur. pmcon2 is not a physical register. reading pmcon2 will read all ' 0 's. the pmcon2 register is used exclusively in the flash memory write sequence. mcp19111 ds22331a-page 104 ? 2013 microchip technology inc. 18.3 flash program memory control registers register 18-1: pmdatl: program memory data low byte register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmdatl<7:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 pmdatl<7:0> : 8 least significant data bits to write or read from program memory register 18-2: pmadrl: program me mory address low byte register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 pmadrl<7:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 pmadrl<7:0> : 8 least significant address bits for program memory read/write operation register 18-3: pmdath: program memory data high byte register u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ?pmdath<5:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-0 pmdath<5:0> : 6 most significant data bits from program memory ? 2013 microchip technology inc. ds22331a-page 105 mcp19111 register 18-4: pmadrh: program memory address high byte register u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 ? ? ? ? pmadrh<3:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3-0 pmadrh<3:0> : specifies the 4 most significant address bits or high bits for program memory reads. register 18-5: pmcon1 ? program memory control register 1 u-1 r/w-0 u-0 u-0 u-0 r/w-0 r/s-0 r/s-0 ? calsel ? ? ?wrenwr rd bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ' 1 ' bit 6 calsel: program memory calibration space select 1 = select test memory area for reads only (for loading calibration trim registers) 0 = select user area for reads bit 5-3 unimplemented: read as ' 0 ' bit 2 wren: program memory write enable bit 1 = allows write cycles 0 = inhibits write to the eeprom bit 1 wr: write control bit 1 = initiates a write cycle to program memory. (the bit is cleared by hardware when write is complete. the wr bit can only be set (not cleared) in software.) 0 = write cycle to the flash memory is complete bit 0 rd: read control bit 1 = initiates a program memory read. (the read takes one cycle. the rd is cleared in hardware; the rd bit can only be set (not cleared) in software). 0 = does not initiate a flash memory read mcp19111 ds22331a-page 106 ? 2013 microchip technology inc. 18.3.1 reading the flash program memory to read a program memory location, the user must write two bytes of the address to the pmadrl and pmadrh registers, and then set control bit rd (pmcon1<0>). once the read control bit is set, the program memory flash controller will use the second instruction cycle after to read the data. this causes the second instruction immediately following the ? bsf pmcon1,rd ? instruction to be ignored. the data is available, in the very next cycle, in the pmdatl and pmdath registers; it can be read as two bytes in the following instructions. pmdatl and pmdath regis- ters will hold this value until another read or until it is written to by the user (during a write operation). example 18-1: flash program read figure 18-1: flash program memory re ad cycle execution ? normal mode bankselpm_adr; change status bits rp1:0 to select bank with pmadr movlwms_prog_pm_addr; movwfpmadrh; ms byte of program address to read movlwls_prog_pm_addr; movwfpmadrl; ls byte of program address to read bankselpmcon1; bank to containing pmcon1 bsf pmcon1, rd; ee read nop ; first instruction after bsf pmcon1,rd executes normally nop ; any instructions here are ignored as program ; memory is read in second cycle after bsf pmcon1,rd ; bankselpmdatl; bank to containing pmadrl movfpmdatl, w; w = ls byte of program pmdatl movfpmdath, w; w = ms byte of program pmdatl q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr (pc + 1) executed here nop executed here pc pc + 1 pmadrh,pmadrl pc+3 pc + 5 flash addr rd bit instr (pc) pmdath,pmdatl instr (pc + 3) pc + 3 pc + 4 instr (pc + 4) instr (pc + 1) instr (pc - 1) executed here instr (pc + 3) executed here instr (pc + 4) executed here flash data pmdath pmdatl register eerhlt ? 2013 microchip technology inc. ds22331a-page 107 mcp19111 18.3.2 writing to the flash program memory a word of the flash program memory may only be written to if the word is in an unprotected segment of memory, as defined in section 12.1 ?configuration word? (bits wrt1:wrt0). flash program memory must be written in four-word blocks. see figures 18-2 and 18-3 for more details. a block consists of four words with sequential addresses, with a lower boundary defined by an address, where pmadrl<1:0> = 00 . all block writes to program memory are done as 16-word erase by four-word write operations. the write operation is edge-aligned and cannot occur across boundaries. to write program data, it must first be loaded into the buffer registers (see figure 18-2 ). this is accomplished by first writing the destination address to pmadrl and pmadrh, and then writing the data to pmdatl and pmdath. after the address and data have been set, then the following sequence of events must be executed: 1. write 55h, then aah, to pmcon2 (flash programming sequence). 2. set the wr control bit of the pmcon1 register. all four buffer register locations should be written to with correct data. if less than four words are being writ- ten to in the block of four words, then a read from the program memory location(s) not being written to must be performed. this takes the data from the program location(s) not being written and loads it into the pmdatl and pmdath registers. then the sequence of events to transfer data to the buffer registers must be executed. to transfer data from the buffer registers to the program memory, the pmadrl and pmadrh must point to the last location in the four-word block (pmadrl<1:0> = 11 ). then the following sequence of events must be executed: 1. write 55h, then aah, to pmcon2 (flash programming sequence). 2. set control bit wr of the pmcon1 register to begin the write operation. the user must follow the same specific sequence to initiate the write for each word in the program block, writing each program word in sequence ( 000 , 001 , 010 , 011 ). when the write is performed on the last word (pmadrl<1:0> = 11 ), a block of sixteen words is automatically erased and the content of the four-word buffer registers are written into the program memory. after the ? bsf pmcon1,wr ? instruction, the processor requires two cycles to set up the erase/write operation. the user must place two nop instructions after the wr bit is set. since data is being written to buffer registers, the writing of the first three words of the block appears to occur immediately. the processor will halt internal operations for the typical 4 ms, only during the cycle in which the erase takes place (i.e., the last word of the sixteen-word block erase). this is not sleep mode, as the clocks and peripherals will continue to run. after the four-word write cycle, the processor will resume operation with the third instruction after the pmcon1 write instruction. the above sequence must be repeated for the higher 12 words. refer to figure 18-2 for a block diagram of the buffer registers and the control signals for test mode. 18.3.3 protection against spurious write there are conditions when the device should not write to the program memory. to protect against spurious writes, various mechanisms have been built in. on power-up, wren is cleared. also, the power-up timer (72 ms duration) prevents program memory writes. the write initiate sequence, and the wren bit, help prevent an accidental write during a power glitch or software malfunction. 18.3.4 operation during code protect when the device is code protected, the cpu is able to read and write unscrambled data to the program memory. the test mode access is disabled. 18.3.5 operation during write protect when the program memory is write protected, the cpu can read and execute from the program memory. the portions of program memory that are write pro- tected can not be modified by the cpu using the pmcon registers. the write protection has no effect in icsp mode. note: the write protect bits are used to protect the users? program from modification by the user?s code. they have no effect when programming is performed by icsp. the code-protect bits, when programmed for code protection, will prevent the program memory from being written via the icsp interface. note: an erase is only initiated for the write of four words, just after a row boundary; or pmcon1 mcp19111 ds22331a-page 108 ? 2013 microchip technology inc. figure 18-2: block writes to 4k flash program memory figure 18-3: flash program memory long write cycle execution 14 14 14 14 program memory buffer register pmadrl<1:0> = 00 buffer register pmadrl<1:0> = 01 buffer register pmadrl<1:0> = 10 buffer register pmadrl<1:0> = 11 pmdatl pmdath 75 07 0 6 8 first word of block to be written if at new row sixteen words of flash are erased, then four buffers are transferred to flash automatically after this word is written q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,wr executed here instr (pc + 1) executed here pc + 1 flash instr pmdath,pmdatl instr (pc+3) instr nop executed here flash flash pmwhlt wr bit processor halted ee write time pmadrh,pmadrl pc + 3 pc + 4 instr (pc + 3) executed here addr data memory location ignored read pc + 2 instr (pc+2) (instr (pc + 2) nop executed here (pc) (pc + 1) ? 2013 microchip technology inc. ds22331a-page 109 mcp19111 19.0 i/o ports in general, when a peripheral is enabled, that pin may not be used as a general purpose i/o pin. each port has two registers for its operation. these registers are: ? trisx registers (data direction register) ? portgpx registers (reads the levels on the pins of the device) some ports may have one or more of the following additional registers. these registers are: ? anselx (analog select) ? wpux (weak pull-up) ports with analog functions also have an anselx register, which can disable the digital input and save power. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 19-1 . figure 19-1: generic i/o portgpx operation example 19-1: initializing porta q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to peripherals anselx v dd v ss ; this code example illustrates ; initializing the portgpa register. the ; other ports are initialized in the same ; manner. banksel portgpa; clrf portgpa;init porta banksel ansela; clrf ansela;digital i/o banksel TRISGPA; movlw b'00011111';set gpa<4:0> as ;inputs movwf TRISGPA;and set gpa<7:6> as ;outputs mcp19111 ds22331a-page 110 ? 2013 microchip technology inc. 19.1 alternate pin function the alternate pin function control (apfcon) register is used to steer specific peripheral input and output functions between different pins. the apfcon register is shown in register 19-1 . for this device family, the following function can be moved between different pins.: ? frequency synchronization clock input/output this bit has no effect on the values of any tris register. port and tris overrides will be routed to the correct pin. the unselected pin will be unaffected. 19.2 portgpa and TRISGPA registers portgpa is an 8-bit wide, bidirectional port consisting of five cmos i/o, two open drain i/o, and one open drain input-only pin. the corresponding data direction register is TRISGPA ( register 19-3 ). setting a TRISGPA bit (= 1 ) will make the corresponding portgpa pin an input (i.e., disable the output driver). clearing a TRISGPA bit (= 0 ) will make the corresponding portgpa pin an output (i.e., enables output driver). the exception is gpa5, which is input only and its TRISGPA bit will always read as ? 1 ?. example 19-1 shows how to initialize an i/o port. reading the portgpa register ( register 19-2 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify- write operations. the TRISGPA register ( register 19-3 ) controls the portgpa pin output drivers, even when they are being used as analog inputs. the user must ensure the bits in the TRISGPA register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. if the pin is configured for a digital output (either port or alternate function), the TRISGPA bit must be cleared in order for the pin to drive the signal, and a read will reflect the state of the pin. 19.2.1 interrupt-on-change each portgpa pin is individually configurable as an interrupt-on-change pin. control bits iocb<7:4> and iocb<2:0> enable or disable the interrupt function for each pin. the interrupt-on-change feature is disabled on a power-on reset. reference section 20.0 ?interrupt-on-change? for more information. 19.2.2 weak pull-ups portgpa <3:0> and portgpa5 have an internal weak pull-up. portgpa<7:6> are special ports for the ssp module and do not have weak pull-ups. individual control bits can enable or disable the internal weak pull-ups (see register 19-4 ). the weak pull-up is automatically turned off when the port pin is configured as an output, an alternative function or on a power-on reset setting the rapu bit of the option register. the weak pull-up on gpa5 is enabled when configured as mclr pin by setting bit 5 of the configuration word, and disabled when gpa5 is an i/o. there is no software control of the mclr pull- up. register 19-1: apfcon: alternate pin function co ntrol register u-0 u-0 u-0 u-0 u-0 u-0 u-0 r/w-0 ? ? ? ? ? ? ? clksel bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 unimplemented: read as ? 0 ? bit 0 clksel: pin selection bit 1 = multi-phase or multiple output clock function is on gpb5 0 = multi-phase or multiple output clock function is on gpa1 ? 2013 microchip technology inc. ds22331a-page 111 mcp19111 19.2.3 ansela register the ansela register ( register 19-5 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as ? 0 ? and allows analog functions on the pin to operate correctly. the state of the ansela bits has no effect on the dig- ital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instruc- tions on the affected port. 19.2.4 portgpa functions and output priorities each portgpa pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 19-1 . for additional information, refer to the appropriate section in this data sheet. portgpa pins gpa7 and gpa4 are true open-drain pins with no connection back to v dd . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown in table 19-1 . note: the ansela bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 19-1: portgpa output priority pin name function priority ( 1 ) gpa0 gpa0 an0 analog_test alt_icspdat1 gpa1 gpa1 an1 clkpin alt_icspclk1 gpa2 gpa2 an2 t0cki int gpa3 gpa3 an3 gpa4 gpa4 (open drain input/output) gpa5 gpa5 (open drain data input only) gpa6 gpa6 alt_icspdat2 gpa7 gpa7 (open drain output) scl alt_icspclk2 note 1: priority listed from highest to lowest. register 19-2: portgpa: portgpa register r/w-x r/w-x r-x r-x r/w-x r/w-x r/w-x r/w-x gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gpa7 : general purpose open drain i/o pin. bit 6 gpa6 : general purpose i/o pin. 1 = port pin is > v ih 0 = port pin is < v il bit 5 gpa5/mclr : general purpose open drain i/o pin. bit 4 gpa7 : general purpose open drain i/o pin. bit 3-0 gpa<3:0> : general purpose i/o pin. 1 = port pin is > v ih 0 = port pin is < v il mcp19111 ds22331a-page 112 ? 2013 microchip technology inc. register 19-3: TRISGPA: po rtgpa tri-state register r/w-1 r/w-1 r-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 trisa<7:6>: portgpa tri-state control bit 1 = portgpa pin configured as an input (tri-stated) 0 = portgpa pin configured as an output bit 5 trisa5: gpa5 port tri-state control bit this bit is always ? 1 ? as gpa5 is an input only bit 4-0 trisa<4:0>: portgpa tri-state control bit 1 = portgpa pin configured as an input (tri-stated) 0 = portgpa pin configured as an output register 19-4: wpugpa: weak pull-up portgpa register u-0 u-0 r/w-1 u-0 r/w-1 r/w-1 r/w-1 r/w-1 ? ? wpua5 ? wpua3 wpua2 wpua1 wpua0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5 wpua5: weak pull-up register bit 1 = pull-up enabled. 0 = pull-up disabled. bit 4 unimplemented: read as ? 0 ? bit 3-0 wpua<3:0>: weak pull-up register bit 1 = pull-up enabled. 0 = pull-up disabled. note 1: the weak pull-up device is enabled only when the global rapu bit is enabled, the pin is in input mode (TRISGPA = 1), and the individual wpua bit is enabled (wpua = 1), and the pin is not configured as an analog input. 2: gpa5 weak pull-up is also enabled when the pin is configured as mclr in configuration word. ? 2013 microchip technology inc. ds22331a-page 113 mcp19111 register 19-5: ansela: anal og select portgpa register u-0 u-0 u-0 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 ? ? ? ? ansa3 ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 unimplemented: read as ? 0 ? bit 3-0 ansa<3:0> : analog select portgpa register bit 1 = analog input. pin is assigned as analog input. ( 1 ) 0 = digital i/o. pin is assigned to port or special function. note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups, and interrupt-on-change if available. the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. table 19-2: summary of regist ers associated with portgpa name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ? ? ansa3 ansa2 ansa1 ansa0 113 apfcon ? ? ? ? ? ? ? clksel 110 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 75 portgpa gpa7 gpa6 gpa5 gpa4 gpa3 gpa2 gpa1 gpa0 111 TRISGPA trisa7 trisa6 trisa5 tri sa4 trisa3 trisa2 trisa1 trisa0 112 wpugpa ? ?wpua5 ? wpua3 wpua2 wpua1 wpua0 112 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portgpa. mcp19111 ds22331a-page 114 ? 2013 microchip technology inc. 19.3 portgpb and trisgpb registers portgpb is an 8-bit wide, bidirectional port consisting of seven general purpose i/o ports. the corresponding data direction register is trisgpb ( register 19-7 ). setting a trisgpb bit (= 1 ) will make the corresponding portgpb pin an input (i.e., disable the output driver). clearing a trisgpb bit (= 0 ) will make the corresponding portgpb pin an output (i.e., enable the output driver). example 19-1 shows how to initialize an i/o port. some pins for portgpb are multiplexed with an alternate function for the peripheral, or a clock function. in general, when a peripheral or clock function is enabled, that pin may not be used as a general purpose i/o pin. reading the portgpb register ( register 19-6 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. the trisgpb register ( register 19-7 ) controls the portgpb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisgpb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. if the pin is configured for a digital output (either port or alternate function), the trisgpb bit must be cleared in order for the pin to drive the signal and a read will reflect the state of the pin. 19.3.1 interrupt-on-change each portgpa pin is individually configurable as an interrupt-on-change pin. control bits iocb<7:4> and iocb<2:0> enable or disable the interrupt function for each pin. the interrupt-on-change feature is disabled on a power-on reset. reference section 20.0 ?interrupt-on-change? for more information. 19.3.2 weak pull-ups each of the portgpb pins has an individually configurable internal weak pull-up. control bits wpub<7:4> and wpub<2:1> enable or disable each pull-up (see register 19-8 ). each weak pull-up is automatically turned off when the port pin is configured as an output. all pull-ups are disabled on a power-on reset by the rapu bit of the option register. 19.3.3 anselb register the anselb register ( register 19-9 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselb bit high will cause all digital reads on the pin to be read as ? 0 ? and allows analog functions on the pin to operate correctly. the state of the anselb bits has no effect on the digital output functions. a pin with trisgpb clear and anselb set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. the trisgpb register ( register 19-7 ) controls the portgpb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisgpb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 19.3.4 portgpb functions and output priorities each portgpb pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 19-3 . for additional information, refer to the appropriate section in this data sheet. portgpb pin gpb0 is a true open drain pin with no connection back to v dd . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc, and some digital input functions are not included in the list below. these inputs are active when the i/o pin is set for analog mode using the anselb registers. digital output functions may control the pin when it is in analog mode, with the priority shown in table 19-3 . note: the anselb bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding anselb bits must be initialized to ? 0 ? by the user?s software. table 19-3: portgpb output priority pin name function priority ( 1 ) gpb0 gpb0 (open drain input/output) sda gpb1 gpb1 an4 eapin gpb2 gpb2 an5 gpb4 gpb4 an6 icspdat icddat gpb5 gpb5 an7 icspclk icdclk alt_clkpin gpb6 gpb6 gpb7 gpb7 note 1: priority listed from highest to lowest. ? 2013 microchip technology inc. ds22331a-page 115 mcp19111 register 19-6: portgp b: portgpb register r/w-x r/w-x r/w-x r/w-x u-x r/w-x r/w-x r/w-x gpb7 gpb6 gpb5 gpb4 ? gpb2 gpb1 gpb0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 gpb<7:4> : general purpose i/o pin bit 1 = port pin is > v ih 0 = port pin is < v il bit 3 unimplemented: read as ? 0 ? bit 2-0 gpb<2:0> : general purpose i/o pin bit 1 = port pin is > v ih 0 = port pin is < v il register 19-7: trisgpb: portgpb tri-state register r/w-1 r/w-1 r/w-1 r/w-1 u-1 r/w-1 r/w-1 r/w-1 trisb7 trisb6 trisb5 trisb4 ? trisb2 trisb1 trisb0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 trisb<7:4>: portgpb tri-state control bit 1 = portgpb pin configured as an input (tri-stated) 0 = portgpb pin configured as an output bit 3 unimplemented: read as ? 1 ? bit 2-0 trisb<2:0>: portgpb tri-state control bit 1 = portgpb pin configured as an input (tri-stated) 0 = portgpb pin configured as an output mcp19111 ds22331a-page 116 ? 2013 microchip technology inc. register 19-8: wpugpb: weak pull-up portgpb register r/w-1 r/w-1 r/w-1 r/w-1 u-0 r/w-1 r/w-1 u-0 wpub7 wpub6 wpub5 wpub4 ? wpub2 wpub1 ? bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 wpub<7:4> : weak pull-up register bit 1 = pull-up enabled 0 = pull-up disabled bit 3 unimplemented: read as ? 0 ? bit 2-1 wpub<2:1> : weak pull-up register bit 1 = pull-up enabled 0 = pull-up disabled bit 0 unimplemented: read as ? 0 ? note 1: the weak pull-up device is enabled only when the global rapu bit is enabled, the pin is in input mode (TRISGPA = 1), the individual wpub bit is enabled (wpub = 1), and the pin is not configured as an analog input. register 19-9: anselb: anal og select portgpb register u-0 u-0 r/w-1 r/w-1 u-0 r/w-1 r/w-1 u-0 ? ? ansb5 ansb4 ? ansb2 ansb1 ? bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ansb<5:4> : analog select portgpb register bit 1 = analog input. pin is assigned as analog input ( 1 ) . 0 = digital i/o. pin is assigned to port or special function. bit 3 unimplemented: read as ? 0 ? bit 2-1 ansb<2:1> : analog select portgpb register bit 1 = analog input. pin is assigned as analog input ( 1 ) . 0 = digital i/o. pin is assigned to port or special function. bit 0 unimplemented: read as ? 0 ? note 1: setting a pin to an analog input automatically disables the digital input circuitry, weak pull-ups and interrupt-on-change if available. the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. ? 2013 microchip technology inc. ds22331a-page 117 mcp19111 table 19-4: summary of regist ers associated with portgpb name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ? ansb2 ansb1 ? 116 apfcon ? ? ? ? ? ? ? clksel 110 option_reg rapu intedg t0cs t0se psa ps2 ps1 ps0 75 portgpb gpb7 gpb6 gpb5 gpb4 ? gpb2 gpb1 gpb0 115 trisgpb trisb7 trisb6 trisb5 trisb4 ? trisb2 trisb1 trisb0 115 wpugpb wpub7 wpub6 wpub5 wpub4 ? wpub2 wpub1 ? 116 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portgpb. mcp19111 ds22331a-page 118 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 119 mcp19111 20.0 interrupt-on-change each portgpa and portgpb pin is individually configurable as an interrupt-on-change pin. control bits ioca and iocb enable or disable the interrupt function for each pin. refer to register 20-1 and register 20-2 . the interrupt-on-change is disabled on a power-on reset. the interrupt-on-change on gpa5 is disabled when configured as mclr pin in the configuration word. for enabled interrupt-on-change pins, the values are compared with the old value latched on the last read of portgpa or portgpb. the mismatched outputs of the last read of all the portgpa and portgpb pins are or?ed together to set the interrupt-on-change interrupt flag bit (iocf) in the intcon register ( register 15-1 ). 20.1 enabling the module to allow individual port pins to generate an interrupt, the iocie bit of the intcon register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 20.2 individual pin configuration to enable a pin to detect an interrupt-on-change, the associated iocax or iocbx bit of the ioca or iocb register is set. 20.3 clearing interrupt flags the user, in the interrupt service routine, clears the interrupt by: a) any read of portgpa or portgpb and clear flag bit iocf. this will end the mismatch condition; or b) any write of portgpa or portgpb and clear flag bit iocf will end the mismatch condition; a mismatch condition will continue to set flag bit iocf. reading portgpa or portgpb will end the mismatch condition and allow flag bit iocf to be cleared. the latch holding the last read value is not affected by a mclr reset. after this reset, the iocf flag will continue to be set if a mismatch is present. 20.4 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the ioce bit is set. note: if a change on the i/o pin should occur when any portgpa or portgpb operation is being executed, then the iocf interrupt flag may not get set. mcp19111 ds22331a-page 120 ? 2013 microchip technology inc. 20.5 interrupt-on-change registers register 20-1: ioca: interrup t-on-change portgpa register r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ioca7 ioca6 ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 ioca<7:6> : interrupt-on-change portgpa register bits. 1 = interrupt-on-change enabled on the pin. 0 = interrupt-on-change disabled on the pin. bit 5 ioca<5> : interrupt-on-change portgpa register bits ( 1 ) . 1 = interrupt-on-change enabled on the pin. 0 = interrupt-on-change disabled on the pin. bit 4-0 ioca<4:0> : interrupt-on-change portgpa register bits. 1 = interrupt-on-change enabled on the pin. 0 = interrupt-on-change disabled on the pin. note 1: the interrupt-on-change on gpa5 is disabled if gpa5 is configured as mclr . register 20-2: iocb: interrup t-on-change portgpb register r/w-0 r/w-0 r/w-0 r/w-0 u-0 r/w-0 r/w-0 r/w-0 iocb7 iocb6 iocb5 iocb4 ? iocb2 iocb1 iocb0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-4 iocb<7:4> : interrupt-on-change portgpb register bits. 1 = interrupt-on-change enabled on the pin. 0 = interrupt-on-change disabled on the pin. bit 3 unimplemented: read as ? 0 ? bit 2-0 iocb<2:0> : interrupt-on-change portgpb register bits. 1 = interrupt-on-change enabled on the pin. 0 = interrupt-on-change disabled on the pin. table 20-1: summary of registers as sociated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ????ansa3ansa2ansa1ansa0 113 anselb ? ? ansb5 ansb4 ? ansb2 ansb1 ? 116 intcon gie peie t0ie inte ioce t0if intf iocf 94 ioca ioca7 ioca6 ioca5 ioca4 ioca3 ioca2 ioca1 ioca0 120 iocb iocb7 iocb6 iocb5 iocb4 ? iocb2 iocb1 iocb0 120 TRISGPA trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 112 trisgpb trisb7 trisb6 trisb5 trisb4 ? trisb2 trisb1 trisb0 115 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by interrupt-on-change. ? 2013 microchip technology inc. ds22331a-page 121 mcp19111 21.0 internal temperature indicator module the mcp19111 is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuit's range of the operating temperature falls between -40c and +125c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. 21.1 circuit operation the tmpsen bit in the abecon register, register 6-15 , is set to enable the internal temperature measurement circuit. the mcp19111 overtemperature shutdown feature is not controlled by this bit. figure 21-1: temperature circuit diagram 21.2 temperature output the output of the circuit is measured using the internal analog-to-digital converter. channel 10 is reserved for the temperature circuit output. refer to section 22.0 ?analog-to-digital converter (adc) module? for detailed information. the temperature of the silicon die can be calculated by the adc measurement by using equation 21-1 . equation 21-1: silicon die temperature tsen adc mux tsrng v dd adc chs bits (adcon0 register) n v out temp_die adc reading 1.75 ? 13.3mv/ ? c ---------------------------------------------------------- - = mcp19111 ds22331a-page 122 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 123 mcp19111 22.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the right justified conversion result into the adc result registers (adresh:adresl register pair). figure 22-1 shows the block diagram of the adc. the internal band gap supplies the voltage reference to the adc. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 22-1: adc block diagram note 1: when adon = 0, all multiplexer inputs are disconnected. 2: see adcon0 register ( register 22-1 ) for detailed analog channel selection per device. 00000 00001 00010 00011 00100 00101 00111 00110 01000 01001 01010 01011 releff adc v out v ref adon go/done chs4:chs0 adresh adresl 10 v ss temp_ana gpa0 v in_ana crt gpb4 vzc v ref ov ref uv ref v bgr ana_in demand gpb2 dci 01100 gpa1 gpa3 gpa2 gpb1 gpb5 10000 10001 10010 10011 10100 10101 10110 10111 mcp19111 ds22331a-page 124 ? 2013 microchip technology inc. 22.1 adc configuration when configuring and using the adc, the following functions must be considered: ? port configuration ? channel selection ? adc conversion clock source ? interrupt control ? result formatting 22.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 19.0 ?i/o ports? for more information. 22.1.2 channel selection there are up to 21 channel selections available: ? an<6:0> pins ? vin: 1/5 of the input voltage (v in ) ?vregref: v out reference voltage ? ov_ref: reference for ov comparator ? uv_ref: reference for uv comparator ? vbgr: band gap reference ? vout: output voltage ? crt: voltage proportional to the ac inductor current ? vzc: an internal ground, voltage for zero current ? demand: input to slope compensation circuitry ? releff: relative efficient measurement channel ? tmp_ana: voltage proportional to silicon die tem- perature ? ana_in: for a multi-phase slave, error amplifier signal received from master ? dci: dc inductor valley current the chs<4:0> bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 22.2 ?adc operation? for more information. 22.1.3 adc conversion clock the source of the conversion clock is software selectable via the adcs bits of the adcon1 register. there are five possible clock options: ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (clock derived from internal oscillator with a divisor of 16) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11 t ad periods as shown in figure 22-2 . for a correct conversion, the appropriate t ad specification must be met. refer to the a/d conversion requirements in section 5.0 ?digital electrical characteristics? for more information. tab l e 2 2- 1 gives examples of appropriate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result. table 22-1: adc clock period (t ad ) vs . device operating frequencies adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 8 mhz f osc /8 001 1.0 s ( 2 ) f osc /16 101 2.0 s f osc /32 010 4.0 s f osc /64 110 8.0 s ( 3 ) f rc x11 2.0 ? 6.0 s ( 1 , 4 ) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 4s for v dd >3.0v. 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: the f rc clock source is only recommended if the conversion will be preformed during sleep. ? 2013 microchip technology inc. ds22331a-page 125 mcp19111 figure 22-2: analog-to-dig ital conversion t ad cycles 22.1.4 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating, or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruction is always executed. if the user is attempting to wake-up from sleep and resume in-line code execution, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. 22.1.5 result formatting the 10-bit a/d conversion result is supplied in right jus- tified format only. figure 22-3 shows the output format. figure 22-3: 10-bit a/d result format t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep-only when the f rc oscillator is selected. (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 read as ? 0 ? 10-bit a/d result mcp19111 ds22331a-page 126 ? 2013 microchip technology inc. 22.2 adc operation 22.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 22.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the adresh:adresl registers with new conversion result 22.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh:adresl registers will not be updated with the partially complete analog-to-digital conversion sample. instead, the adresh:adresl register pair will retain the value of the previous conversion. additionally, a two t ad delay is required before another acquisition can be initiated. following the delay, an input acquisition is automatically started on the selected channel. 22.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc clock source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conversion to be aborted and the adc module is turned off, although the adon bit remains set. 22.2.5 a/d conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? select adc input channel ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt ( 1 ) 4. wait the required acquisition time ( 2 ) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result. 8. clear the adc interrupt flag (required if interrupt is enabled). example 22-1: a/d conversion note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 22.2.5 ?a/d conversion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 22.4 ?a/d acquisition requirements? . ;this code block configures the adc ;for polling, frc clock and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?01110000? ;frc clock movwf adcon1 ; banksel TRISGPA ; bsf TRISGPA,0 ;set gpa0 to input banksel ansela ; bsf ansela,0 ;set gpa0 to analog banksel adcon0 ; movlw b?01000001? ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,1 ;start conversion btfsc adcon0,1 ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adresl ; movf adresl,w ;read lower 8 bits movwf resultlo ;store in gpr space ? 2013 microchip technology inc. ds22331a-page 127 mcp19111 22.3 adc register definitions the following registers are used to control the operation of the adc: register 22-1: adcon0: a/ d control register 0 u-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 ? chs4 chs3 chs2 chs1 chs0 go/done adon bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 00000 = vin_ana (analog voltage proportional to v in ) 00001 = vregref (reference voltage for v reg output) 00010 = ov_ref (reference for overvoltage comparator) 00011 = uv_ref (reference for undervoltage comparator) 00100 = vbgr (band gap reference) 00101 = int_vreg (internal version of the v reg load voltage) 00110 = crt (voltage proportional to the current in the inductor) 00111 = vzc (an internal ground, voltage for zero current) 01000 = demand (input to current loop, output of demand mux) 01001 = releff (analog voltage proportional to duty cycle) 01010 = tmp_ana (analog voltage proportional to temperature) 01011 = ana_in (demanded current from the remote master) 01100 = dci (dc inductor valley current) 01101 = unimplemented 01110 = unimplemented 01111 = unimplemented 10000 = gpa0 (i.e. addr1) 10001 = gpa1 (i.e. addr0) 10010 = gpa2 (i.e. temperature sensor input) 10011 = gpa3 (i.e. tracking voltage) 10100 = gpb1 10101 = gpb2 10110 = gpb4 10111 = gpb5 11000 = unimplemented 11001 = unimplemented 11011 = unimplemented 11100 = unimplemented 11101 = unimplemented 11110 = unimplemented 11111 = unimplemented bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current mcp19111 ds22331a-page 128 ? 2013 microchip technology inc. register 22-2: adcon1: a/ d control register 1 u-0 r/w-0 r/w-0 r/w-0 u-0 u-0 u-0 u-0 ? adcs2 adcs1 adcs0 ? ? ? ? bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 unimplemented: read as ? 0 ? bit 6-4 adcs<2:0>: a/d conversion clock select bits 000 = reserved 001 =f osc /8 010 =f osc /32 x11 =f rc (clock derived from internal oscillator with a divisor of 16) 100 = reserved 101 =f osc /16 110 =f osc /64 bit 3-0 unimplemented: read as ? 0 ? register 22-3: adresh: adc result register high (adresh) u-0 u-0 u-0 u-0 u-0 u-0 r-x r-x ? ? ? ? ? ? adres9 adres8 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-2 unimplemented: read as ? 0 ? bit 1-0 adres<9:8> : most significant a/d results register 22-4: adresl: adc result register low (adresl) r-x r-x r-x r-x r-x r-x r-x r-x adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-0 adres<7:0> : least significant a/d results ? 2013 microchip technology inc. ds22331a-page 129 mcp19111 22.4 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 22-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 22-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 22-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 22-1: acquisition time example note 1: the charge holding capacitor (c hold ) is not discharged after each conversion. 2: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification. t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2 s t c temperature - 25c ?? 0.05 s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/2047) ? = 10 pf 1 k ? 7 k ? 10 k ? ++ ?? ? ln(0.0004885) = 1.37 =s v applied 1e t c ? rc ---------- ? ?? ?? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? ----------------------------- - ? ?? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? ----------------------------- - ? ?? ?? ?? v chold = v applied 1e t c ? rc ---------- ? ?? ?? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ; [2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature +50c and external impedance of 10 k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2 s 1.37s 50c- 25c ?? 0.05s/c ?? ?? ++ = 4.67 s = mcp19111 ds22331a-page 130 ? 2013 microchip technology inc. figure 22-4: analog input model figure 22-5: adc transfer function c pin va r s analog 5pf v dd v t ? 0.6v v t ? 0.6v i leakage ( 1 ) r ic ? 1k sampling switch ss r ss c hold = 10 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd r ss input pin legend: note 1: refer to section 5.0 ?digital electrical characteristics? . c hold = sample/hold capacitance c pin = input capacitance i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r ss = resistance of sampling switch ss = sampling switch v t = threshold voltage 3ffh 3feh adc output code 3fdh 3fch 03h 02h 01h 00h full-scale 3fbh 0.5 lsb v ref - zero-scale transition v ref + transition 1.5 lsb full-scale range analog input voltage ? 2013 microchip technology inc. ds22331a-page 131 mcp19111 table 22-2: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs4 chs3 chs2 chs1 chs0 go/done adon 127 adcon1 ? adcs2 adcs1 adcs0 ? ? ? ? 128 adresh ? ? ? ? ? ? adres9 adres8 128 adresl adres7 adres6 adres5 adres4 adres3 adres2 adres1 adres0 128 ansela ? ? ? ? ansa3 ansa2 ansa1 ansa0 113 anselb ? ? ansb5 ansb4 ? ansb2 ansb1 ? 116 intcon gie peie t0ie inte ioce t0if intf iocf 93 pie1 ?adie bclie sspie ? ? tmr2ie tmr1ie 94 pir1 ?adif bclif sspif ? ? tmr2if tmr1if 96 TRISGPA trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 112 trisgpb trisb7 trisb6 trisb5 trisb4 ? trisb2 trisb1 trisb0 115 legend: ? = unimplemented read as ? 0 ?. shaded cells are not used for adc module. mcp19111 ds22331a-page 132 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 133 mcp19111 23.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 8-bit prescaler (independent of watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow figure 23-1 is a block diagram of the timer0 module. figure 23-1: block diagra m of the timer0 23.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 23.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the t0cs bit of the option_reg register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 23.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on every rising or falling edge of the t0cki pin. the incrementing edge is determined by the t0se bit of the option_reg register. 8-bit counter mode using the t0cki pin is selected by setting the t0cs bit in the option_reg register to ? 1 ?. 23.1.3 software programmable prescaler a single software programmable prescaler is available for use with either timer0 or the watchdog timer (wdt), but not both simultaneously. the prescaler assignment is controlled by the psa bit of the option_reg register. to assign the prescaler to timer0, the psa bit must be cleared to ? 0 ?. there are 8 prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option_reg register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be disabled by setting the psa bit of the option_reg register. the prescaler is not readable or writable. when assigned to the timer0 module, all instructions writing to the tmr0 register will clear the prescaler. t0cki tmr0se tmr0 ps<2:0> data bus set flag bit tmr0if on overflow tmr0cs 0 1 0 1 8 8 8-bit prescaler f osc /4 psa sync 2 t cy overflow to timer1 note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. mcp19111 ds22331a-page 134 ? 2013 microchip technology inc. 23.1.4 switching prescaler between timer0 and wdt modules as a result of having the prescaler assigned to either timer0 or the wdt, it is possible to generate an unintended device reset when switching prescaler values. when changing the prescaler assignment from timer0 to the wdt module, the instruction sequence shown in example 23-1 must be executed. example 23-1: changing prescaler (timer0 ? wdt) when changing the prescaler assignment from the wdt to the timer0 module, the following instruction sequence must be executed (see example 23-2 ). example 23-2: changing prescaler (wdt ? timer0) 23.1.5 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the t0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the t0if bit can only be cleared in software. the timer0 interrupt enable is the t0ie bit of the intcon register. 23.1.6 using timer0 with an external clock when timer0 is in counter mode, the synchronization of the t0cki input and the timer0 register is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks. therefore, the high and low periods of the external clock source must meet the timing requirements as shown in section 5.0 ?digital electrical characteristics? . 23.1.7 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. banksel tmr0 ; clrwdt ;clear wdt clrf tmr0 ;clear tmr0 and ;prescaler banksel option_reg ; bsf option_reg,psa ;select wdt clrwdt ; ; movlw b?11111000? ;mask prescaler andwf option_reg,w ;bits iorlw b?00000101? ;set wdt prescaler movwf option_reg ;to 1:32 clrwdt ;clear wdt and ;prescaler banksel option_reg ; movlw b?11110000? ;mask tmr0 select and andwf option_reg,w ;prescaler bits iorlw b?00000011? ;set prescale to 1:16 movwf option_reg ; note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep. table 23-1: summary of registers associated with timer0 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie t0ie inte iocie t0if intf iocif 94 option_reg raup intedg t0cs t0se psa ps2 ps1 ps0 75 tmr0 timer0 module register 133* TRISGPA trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 112 legend: ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by the timer0 module. * page provides register information. ? 2013 microchip technology inc. ds22331a-page 135 mcp19111 24.0 timer1 module with gate control the timer1 module is a 16-bit timer with the following features: ? 16-bit timer register pair (tmr1h:tmr1l) ? readable and writable (both registers) ? selectable internal clock source ? 2-bit prescaler ? interrupt on overflow figure 24-1 is a block diagram of the timer1 module. figure 24-1: timer1 block diagram 24.1 timer1 operation the timer1 module is a 16-bit incrementing timer which is accessed through the tmr1h:tmr1l register pair. writes to tmr1h or tmr1l directly update the counter. the timer is incremented on every instruction cycle. timer1 is enabled by configuring the tmr1on bit in the t1con register. table 24-1 displays the timer1 enable selections. 24.2 clock source selection the tmr1cs bit of the t1con register is used to select the clock source for timer1. tab l e 2 4- 1 displays the clock source selections. 24.2.1 internal clock source the tmr1h:tmr1l register pair will increment on multiples of f osc or f osc /4 as determined by the timer1 prescaler. as an example, when the f osc internal clock source is selected, the timer1 register value will increment by four counts every instruction clock cycle. tmr1h tmr1l tmr1cs t1ckps<1:0> prescaler 1, 2, 4, 8 1 0 2 set flag bit tmr1if on overflow tmr1 ( 1 ) tmr1on note 1: tmr1 register increments on rising edge. f osc f osc /4 table 24-1: clock source selections tmr1cs clock source 1 8 mhz system clock (f osc ) 0 2 mhz instruction clock (f osc /4) mcp19111 ds22331a-page 136 ? 2013 microchip technology inc. 24.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits of the t1con register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 24.4 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: ? tmr1on bit of the t1con register ? tmr1ie bit of the pie1 register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt is cleared by clearing the tmr1if bit in the interrupt service routine. 24.5 timer1 in sleep unlike other standard mid-range timer1 modules, the mcp19111 timer1 module only clocks from an internal system clock, and thus does not run during sleep mode, nor can be used to wake the device from this mode. 24.6 timer1 control register the timer1 control register (t1con), shown in register 24-1 , is used to control timer1 and select the various features of the timer1 module. note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. register 24-1: t1con: ti mer1 control register u-0 u-0 r/w-0 r/w-0 u-0 u-0 r/w-0/ r/w-0 ? ? t1ckps1 t1ckps0 ? ? tmr1cs tmr1on bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-6 unimplemented: read as ? 0 ? bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3-2 unimplemented: read as ? 0 ? bit 1 tmr1cs: timer1 clock source control bit 1 = 8 mhz system clock (f osc ) 0 = 2 mhz instruction clock (f osc ) bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 =stops timer1 clears timer1 gate flip-flop ? 2013 microchip technology inc. ds22331a-page 137 mcp19111 table 24-2: summary of registers associated with timer1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie t0ie inte ioce t0if intf iocf 93 pie1 ? adie bclie sspie ? ? tmr2ie tmr1ie 94 pir1 ? adif bclif sspif ? ? tmr2if tmr1if 96 tmr1h holding register for the most significant byte of the 16-bit tmr1 register 135* tmr1l holding register for the least significant byte of the 16-bit tmr1 register 135* t1con ? ? t1ckps1 t1ckps0 ? ? tmr1cs tmr1on 136 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. * page provides register information. mcp19111 ds22331a-page 138 ? 2013 microchip technology inc. 25.0 timer2 module the timer2 module is an 8-bit timer with the following features: ? 8-bit timer register (tmr2) ? 8-bit period register (pr2) ? interrupt on tmr2 match with pr2 ? software programmable prescaler (1:1, 1:4, 1:16) see figure 25-1 for a block diagram of timer2. 25.1 timer2 operation the clock input to the timer2 module is the system clock (f osc ). the clock is fed into the timer2 prescaler, which has prescale options of 1:1, 1:4 or 1:16. the output of the prescaler is then used to increment the tmr2 register. the values of tmr2 and pr2 are constantly compared to determine when they match. tmr2 will increment from 00h until it matches the value in pr2. when a match occurs, tmr2 is reset to 00h on the next increment cycle. the match output of the timer2/pr2 comparator is used to set the tmr2if interrupt flag bit in the pir1 register. the tmr2 and pr2 registers are both fully readable and writable. on any reset, the tmr2 register is set to 00h and the pr2 register is set to ffh. timer2 is turned on by setting the tmr2on bit in the t2con register to a ? 1 ?. timer2 is turned off by clearing the tmr2on bit to a ? 0 ?. the timer2 prescaler is controlled by the t2ckps bits in the t2con register. the prescaler counter are cleared when: ? a write to tmr2 occurs. ? a write to t2con occurs. ? any device reset occurs (power-on reset, mclr reset, watchdog timer reset, or brown-out reset). figure 25-1: timer2 block diagram note: tmr2 is not cleared when t2con is written. comparator tmr2 sets flag tmr2 output reset prescaler pr2 2 f osc 1:1, 1:4, 1:8, 1:16 eq bit tmr2if t2ckps<1:0> ? 2013 microchip technology inc. ds22331a-page 139 mcp19111 25.2 timer2 control register register 25-1: t2con: ti mer2 control register u-0 u-0 u-0 u-0 u-0 r/w-0 r/w-0 r/w-0 ? ? ? ? ? tmr2on t2ckps1 t2ckps0 bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-3 unimplemented: read as ? 0 ? bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 =prescaler is 1 01 =prescaler is 4 10 =prescaler is 8 11 =prescaler is 16 table 25-1: summary of registers associated with timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie t0ie inte ioce t0if intf iocf 93 pie1 ? adie bclie sspie ? ?tmr2ie tmr1ie 94 pir1 ? adif bclif sspif ? ?tmr2if tmr1if 96 pr2 timer2 module period register 138* t2con ? ? ? ? ? tmr2on t2ckps1 t2ckps0 139 tmr2 holding register for the 8-bit tmr2 time base 138* legend: ? = unimplemented read as ? 0 ?. shaded cells are not used for timer2 module. * page provides register information. mcp19111 ds22331a-page 140 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 141 mcp19111 26.0 pwm module the ccp module implemented on the mcp19111 is a modified version of the ccp module found in standard mid-range microcontrollers. in the mcp19111, the pwm module is used to generate the system clock or system oscillator. this system clock will control the mcp19111 switching frequency, as well as set the maximum allowable duty cycle. the pwm module does not continuously adjust the duty cycle to control the output voltage. this is accomplished by the analog control loop and associated circuitry. 26.1 standard pulse-width modulation (pwm) mode the pwm module output signal is used to set the operating switching frequency and maximum allowable duty cycle of the mcp19111. the actual duty cycle on the hdrv and ldrv is controlled by the analog pwm control loop. however, this duty cycle cannot be greater than the value in the pwmrl register. there are two modes of operation that concern the system clock pwm signal. these modes are stand-alone (non-frequency synchronization) and frequency synchronization. 26.1.1 stand-alone (non-frequency synchronization) mode when the mcp19111 is running stand-alone, the pwm signal functions as the system clock. it is operating at the programmed switching frequency with a programmed maximum duty cycle (d clock ). the programmed maximum duty cycle is not adjusted on a cycle-by-cycle basis to control the mcp19111 system output. the required duty cycle (d buck ) to control the output is adjusted by the mcp19111 analog control loop and associated circuitry. d clock does, however, set the maximum allowable d buck . equation 26-1: 26.1.2 switching frequency synchronization mode the mcp19111 can be programmed to be a switching frequency master or slave device. the master device functions as described in section 26.1.1 ?stand-alone (non-frequency synchronization) mode? with the exception of the system clock also being applied to gpa1. a slave device will receive the master system clock on gpa1. this master system clock will be or?ed with the output of the timer2 module. this or?ed signal will latch pwmrl into pwmrh and pwmphl into pwmphh. figure 26-1 shows a simplified block diagram of the ccp module in pwm mode. the pwmphl register allows for a phase shift to be added to the slave system clock. it is desired to have the mcp19111 slave devices system clock start point shifted by a programmed amount from the master system clock. this slave phase shift is specified by writing to the pwmphl reg- ister. the slave phase shift can be calculated by using the following equation. equation 26-2: d buck 1d clock ? ? slave phase shift =pwmphl?t osc? (t2 prescale value ) mcp19111 ds22331a-page 142 ? 2013 microchip technology inc. figure 26-1: simplified pwm block diagram a pwm output ( figure 26-2 ) has a time base (period) and a time that the output stays high (duty cycle). the frequency of the pwm is the inverse of the period (1/period). figure 26-2: pwm output 26.1.3 pwm period the pwm period is specified by writing to the pr2 register. the pwm period can be calculated using the following equation: equation 26-3: when tmr2 is equal to pr2, the following two events occur on the next increment cycle: ?tmr2 is cleared ? the pwm duty cycle is latched from pwmrl into pwmrh clkpin_in r sq q osc system clock latch data latch data reset timer 8 8 8 8 comparator comparator comparator tmr2 (note 1) 8 8 8 8 pr2 pwmphl pwmrl pwmrh (slave) pwmphh (slave) note 1: timer 2 should be clocked by f osc (8 mhz). period duty cycle tmr2 = pr2 + 1 tmr2 = pwmrh tmr2 = pr2 + 1 pwm period =[(pr2)+1] x t osc x(t2 prescale value ) ? 2013 microchip technology inc. ds22331a-page 143 mcp19111 26.1.4 pwm duty cycle (d clock ) the pwm duty cycle (d clock ) is specified by writing to the pwmrl register. up to 8-bit resolution is available. the following equation is used to calculate the pwm duty cycle (d clock ): equation 26-4: the pwmrl bits can be written to at any time, but the duty cycle value is not latched into pwmrh until after a match between pr2 and tmr2 occurs. 26.2 operation during sleep when the device is placed in sleep, the allocated timer will not increment and the state of the module will not change. if the clkpin pin is driving a value, it will continue to drive that value. when the device wakes up, it will continue from this state. pwm duty cycle =pwmrl x t osc x(t2 prescale value ) table 26-1: summary of register s associated with pwm module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon ? ? ? ? ? ? ? clksel 110 t2con ? ? ? ? ? tmr2on t2ckps1 t2ckps0 139 pr2 timer2 module period register 138* pwmrl pwm register low byte 141* pwmphl slave phase shift byte 141* buffcon mltph2 mltph1 mltph0 asel4 asel3 asel2 asel1 asel0 56 legend: ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by capture mode. * page provides register information. mcp19111 ds22331a-page 144 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 145 mcp19111 27.0 master synchronous serial port (mssp) module 27.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module only operates in inter-integrated circuit (i 2 c) mode. ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c) the i 2 c interface supports the following modes and features: ?master mode ? slave mode ? byte nacking (slave mode) ? limited multi-master support ? 7-bit and 10-bit addressing ? start and stop interrupts ? interrupt masking ? clock stretching ? bus collision detection ? general call address matching ? dual address masking ? address hold and data hold modes ? selectable sda hold times figure 27-1 is a block diagram of the i 2 c interface module in master mode. figure 27-2 is a diagram of the i 2 c interface module in slave mode. figure 27-1: mssp block diagram (i 2 c master mode) read write sspsr start bit, stop bit, start bit detect, sspbuf internal data bus set/reset: s, p, sspstat, wcol, sspxov shift clock msb lsb sda acknowledge generate (sspcon2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [sspm 3:0] baud rate reset sen, pen (sspcon2) generator (sspadd) address match detect set sspif, bclif mcp19111 ds22331a-page 146 ? 2013 microchip technology inc. figure 27-2: mssp block diagram (i 2 c slave mode) 27.2 i 2 c mode overview the inter-integrated circuit bus (i 2 c) is a multi-master serial data communication bus. devices communicate in a master/slave environment, where the master devices initiate the communication. a slave device is controlled through addressing. the mssp module has eight registers for i 2 c operation. they are the: ? mssp status register (sspstat) ? mssp control register1 (sspcon1) ? mssp control register2 (sspcon2) ? mssp control register3 (sppcon3) ? serial receive/transmit buffer (sspbuf) ? mssp shift register (sspsr) - not directly accessible ? mssp address register (sspadd) ? mssp address register2 (sspadd2) ? mssp address mask register1 (sspmsk) ? mssp address mask register2 (sspmsk2) the sspcon1 register is used to define the i 2 c mode. four selection bits (sspcon1<3:0>) allow one of the following i 2 c modes to be selected: ?i 2 c slave mode (7-bit address) ?i 2 c slave mode (10-bit address) ?i 2 c master mode, clock = osc/4 (sspadd +1) ?i 2 c firmware controlled master mode (slave idle) the sspstat register gives the status of the data transfer. this information includes detection of a start or stop bit, specifies if the data received byte was data or address, if the next byte is completion of the 10-bit address, and if this will be a read or write data transfer. the sspbuf is the register to which transfer data is written to or read from. the sspsr register shifts the data in or out of the device. in receive operation, the sspbuf and sspsr create a double buffer receiver. this allows reception of the next byte to begin before reading the last byte of received data. when the complete byte is received before the sspbuf register is read, a receiver overflow has occurred and the sspov bit (sspcon1<6>) is set and the byte in the sspsr is lost. read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl sda shift clock msb lsb sspmsk reg ? 2013 microchip technology inc. ds22331a-page 147 mcp19111 the i 2 c bus specifies two signal connections: ? serial clock (scl) ? serial data (sda) both the scl and sda connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero; letting the line float is considered a logical one. before selecting any i 2 c mode, the scl and sda pins must be programmed to inputs by setting the appropriate tris bits. selecting i 2 c mode, by setting the sspen bit, enables the scl and sda pins to be used as clock and data lines in i 2 c mode. figure 27-3 shows a typical connection between two devices configured as master and slave. figure 27-3: i 2 c master/slave connection the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: ? master transmit mode (master is transmitting data to a slave) ? master receive mode (master is receiving data from a slave) ?slave transmit mode (slave is transmitting data to a master) ? slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a single read/write bit, which determines whether the master intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the complement, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sda line while the scl line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. the acknowledge bit (ack ) is an active-low signal, which holds the sda line low to indicate to the transmitter that the slave device has received the transmitted data and is ready to receive more. the transition of a data bit is always performed while the scl line is held low. transitions that occur while the scl line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeatedly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode, and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this example, the master device is in master receive mode, and the slave is slave transmit mode. on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indicated by a low-to-high transition of the sda line, while the scl line is held high. in some cases, the master may want to maintain control of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols: ? single message where a master writes data to a slave ? single message where a master reads data from a slave ? combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the scl line, is called clock stretching. clock stretching gives slave devices a mechanism to control the flow of data. when this detection is used on the sda line, it is called arbitration. arbitration ensures that there is only one master device communicating at any single time. master scl sda scl sda slave v dd v dd mcp19111 ds22331a-page 148 ? 2013 microchip technology inc. 27.2.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the scl clock line low after receiving or sending a bit, indicating that it is not yet ready to continue. the master that is communicating with the slave will attempt to raise the scl line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the scl connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 27.2.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a transmission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sda data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels don't match, loses arbitration, and must stop transmitting on the sda line. for example, if one transmitter holds the sda line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sda line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sda line. if this transmitter is also a master device, it also must stop driving the scl line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sda line continues with it's original transmission. it can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. if two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. arbitration usually occurs very rarely, but it is a neces- sary process for proper multi-master support. 27.3 i 2 c mode operation all mssp i 2 c communication is byte oriented and shifted out msb first. six sfr registers and two interrupt flags interface the module with the pic microcontroller and user software. two pins, sda and scl, are exercised by the module to communicate with other external i 2 c devices. 27.3.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, fol- lowed by an acknowledge bit sent back. after the 8 th falling edge of the scl line, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, scl, is provided by the master. data is valid to change while the scl signal is low, and sampled on the rising edge of the clock. changes on the sda line while the scl line is high define special conditions on the bus, explained below. 27.3.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explanation. this table was adapted from the philips i 2 c specification. 27.3.3 sda and scl pins on the mcp19111, the scl and sda pins are always open-drain. these pins should be set by the user to inputs by setting the appropriate tris bits. note: data is tied to output zero when an i 2 c mode is enabled. ? 2013 microchip technology inc. ds22331a-page 149 mcp19111 27.3.4 sda hold time the hold time of the sda pin is selected by the sdaht bit of the sspcon3 register. hold time is the time sda is held valid after the falling edge of scl. setting the sdaht bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. 27.3.5 start condition the i 2 c specification defines a start condition as a transition of sda from a high to a low state, while scl line is high. a start condition is always generated by the master and signifies the transition of the bus from an idle to an active state. figure 27-4 shows the wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sda line low before asserting it low. this does not conform to the i 2 c specification, that states no bus collision can occur on a start. 27.3.6 stop condition a stop condition is a transition of the sda line from low-to-high state while the scl line is high. 27.3.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. in 10-bit addressing slave mode, a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, match- ing both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained. until a stop condition, a high address with r/w clear or a high address match fails. table 27-1: i 2 c bus terms term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and terminates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sda and scl lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in sspaddx. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus hold scl low to stall communication. bus collision any time the sda line is sampled low by the module while it is outputting and expected high state. note: at least one scl low time must appear before a stop is valid, therefore, if the sda line goes low then high again while the scl line stays high, only the start condition is detected. mcp19111 ds22331a-page 150 ? 2013 microchip technology inc. 27.3.8 start/stop condition interrupt masking the scie and pcie bits of the sspcon3 register can enable the generation of an interrupt in slave modes that do not typically support this function. these bits will have no effect on slave modes where interrupt on start and stop detect are already enabled. figure 27-4: i 2 c start and stop conditions figure 27-5: i 2 c restart condition 27.3.9 acknowledge sequence the 9 th scl pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sda line low. the transmitter must release control of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pulling the sdax line low indicates to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the sspcon2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the sspcon2 regis- ter is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the sspcon3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the sspstat register or the sspov bit of the sspcon1 register are set when a byte is received, an ack will not be sent. when the module is addressed, after the 8 th falling edge of scl on the bus, the acktim bit of the sspcon3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim status bit is only active when the ahen bit or dhen bit is enabled. sda scl p stop condition s start condition change of data allowed change of data allowed restart condition sr change of data allowed change of data allowed ? 2013 microchip technology inc. ds22331a-page 151 mcp19111 27.4 i 2 c slave mode operation the mssp slave mode operates in one of the four modes selected in the sspm bits of sspcon1 register. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing mode operate the same as 7-bit, with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operate the same as the other modes. the exception is the sspif bit getting set upon detection of a start, restart or stop condition. 27.4.1 slave mode addresses, sspadd the sspadd register ( register 27-7 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspbuf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the software that anything happened. the sspmsk register ( register 27-6 ) affects the address matching process. see section 27.4.10 ?sspmskx register? for more information. 27.4.2 second slave mode address, sspadd2 the sspadd2 register ( register 27-9 ) contains a second slave mode address. to enable the use of this second slave mode address, bit 0 must be set. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspbuf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the software that anything happened. the sspmsk2 register, register 27-8 , affects the address matching process. see section 27.4.10 ?sspmskx register? for more information. 27.4.2.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 27.4.2.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of ?1 1 1 1 0 a9 a8 0?. a9 and a8 are the two msb of the 10-bit address and stored in bits 2 and 1 of the sspaddx register. after the acknowledge of the high byte the ua bit is set and scl is held low until the user updates sspaddx with the low address. the low address byte is clocked in and all 8 bits are compared to the low address value in sspaddx. even if there is not an address match; sspif and ua are set, and scl is held low until sspaddx is updated to receive a high byte again. when sspaddx is updated, the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communication. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hardware will then acknowledge the read request and prepare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match. 27.4.3 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and acknowledged. when an overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf of the sspstat register is set, or bit sspov of the sspcon1 register is set. the boen bit of the sspcon3 register modifies this operation. for more information, see register 27-5 . an mssp interrupt is generated for each transferred data byte. flag bit, sspif, must be cleared by software. when the sen bit of the sspcon2 register is set, scl will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the sspcon1 register, except sometimes in 10-bit mode. mcp19111 ds22331a-page 152 ? 2013 microchip technology inc. 27.4.3.1 7-bit addressing reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 7-bit addressing mode, all decisions made by hardware or software and their effect on reception. figure 27-6 and figure 27-7 are used as a visual reference for this description. this is a step-by-step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sda low sending an ack to the master, and sets sspif bit. 5. software clears the sspif bit. 6. software reads received address from sspbuf clearing the bf flag. 7. if sen = 1 , slave software sets ckp bit to release the scl line. 8. the master clocks out a data byte. 9. slave drives sda low sending an ack to the master, and sets sspif bit. 10. software clears sspif. 11. software reads the received byte from sspbuf clearing bf. 12. steps 8?12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of sspstat, and the bus goes idle. 27.4.3.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operates the same as without these options with extra interrupts and clock stretching added after the 8 th falling edge of scl. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hardware. this functionality adds support for pmbus that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communication. figure 27-8 displays a module using both address and data holding. figure 27-9 includes the operation with the sen bit of the sspcon2 register set. 1. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. sspif is set and ckp cleared after the 8 th falling edge of scl. 3. slave clears the sspif. 4. slave can look at the acktim bit of the sspcon3 register to determine if the sspif was after or before the ack. 5. slave reads the address value from sspbuf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. sspxif is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears sspif. 11. sspif set and ckp cleared after 8th falling edge of scl for a received data byte. 12. slave looks at acktim bit of sspcon3 to determine the source of the interrupt. 13. slave reads the received data from sspbuf clearing bf. 14. steps 7?14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and interrupt on stop detect is disabled, the slave will only know by polling the p bit of the sststat register. note: sspif is still set after the 9th falling edge of scl even if there is no clock stretching and bf has been cleared. only if nack is sent to master is sspif not set. ? 2013 microchip technology inc. ds22331a-page 153 mcp19111 figure 27-6: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf sspov 12345678 12345 67 8 1 2 3 4 5 678 9 9 9 ack is not sent. sspov set because sspbuf is still full. cleared by software first byte of data is available in sspbuf sspbuf is read sspif set on 9th falling edge of scl cleared by software p bus master sends stop condition s from slave to master mcp19111 ds22331a-page 154 ? 2013 microchip technology inc. figure 27-7: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl 123456789 123456789 123456789 p sspif set on 9th scl is not held ckp is written to 1 in software, ckp is written to ? 1 ? in software, ack low because falling edge of scl releasing scl ack is not sent. bus master sends ckp sspov bf sspif sspov set because sspbuf is still full. cleared by software first byte of data is available in sspbuf ack = 1 cleared by software sspbuf is read clock is held low until ckp is set to ? 1 ? releasing scl stop condition s ack ack receive address receive data receive data r/w= 0 ? 2013 microchip technology inc. ds22331a-page 155 mcp19111 figure 27-8: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl bf ckp s p 12 3 456 7 8 9 12345678 9 12345678 master sends stop condition s data is read from sspbuf cleared by software sspif is set on 9th falling edge of scl, after ack ckp set by software, scl is released slave software 9 acktim cleared by hardware in 9th rising edge of scl sets ackdt to not ack when dhen=1: ckp is cleared by hardware on 8th falling edge of scl slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of scl when ahen=1: ckp is cleared by hardware and scl is stretched address is read from ssbuf acktim set by hardware on 8th falling edge of scl ack master releases sdax to slave for ack sequence no interrupt after not ack from slave ack =1 ack ackdt acktim sspif if ahen = 1 : sspif is set mcp19111 ds22331a-page 156 ? 2013 microchip technology inc. figure 27-9: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ackdt ckp s p ack s 12 34 5678 9 12 3 4567 8 9 12 34 5 67 8 9 ack ack cleared by software acktim is cleared by hardware sspbuf can be set by software, read any time before next byte is loaded release scl on 9th rising edge of scl received address is loaded into sspbuf slave software clears ackdt to ack r/w = 0 master releases sda to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl when dhen = 1 ; on the 8th falling edge of scl of a received data byte, ckp is cleared received data is available on sspbuf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim ? 2013 microchip technology inc. ds22331a-page 157 mcp19111 27.4.4 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the scl pin is held low (see section 27.4.7 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then the scl pin should be released by setting the ckp bit of the sspcon1 register. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. this ack value is copied to the ackstat bit of the sspcon2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, the scl pin must be released by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared by software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. 27.4.4.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sda line. if a bus collision is detected and the sbcde bit of the sspcon3 register is set, the bclif bit of the pir register is set. once a bus collision is detected, the slave goes idle and waits to be addressed again. user software can use the bclif bit to handle a slave bus collision. 27.4.4.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 27-10 can be used as a reference to this list. 1. master sends a start condition on sda and scl. 2. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting sspif bit. 4. slave hardware generates an ack and sets sspif. 5. sspif bit is cleared by user. 6. software reads the received address from ssp- buf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into sspbuf. 9. ckp bit is set releasing scl, allowing the master to clock the data out of the slave. 10. sspif is set after the ack response from the master is loaded into the ackstat register. 11. sspif bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but sspif is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of scl (9th) rather than the falling. mcp19111 ds22331a-page 158 ? 2013 microchip technology inc. figure 27-10: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ckp ackstat r/w d/a s p received address when r/w is set r/w is copied from the indicates an address is read from sspbuf scl is always held low after 9th scl falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition ? 2013 microchip technology inc. ds22331a-page 159 mcp19111 27.4.4.3 7-bit transmission with address hold enabled setting the ahen bit of the sspcon3 register enables additional clock stretching and interrupt generation after the 8 th falling edge of a received matching address. once a matching address has been clocked in, ckp is cleared and the sspif interrupt is set. figure 27-11 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the 8 th falling edge of the scl line, the ckp bit is cleared and sspif interrupt is generated. 4. slave software clears sspif. 5. slave software reads acktim bit of sspcon3 register, and r/w and d/a of the sspstat register to determine the source of the interrupt. 6. slave reads the address value from the sspbuf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets ackdt bit of the sspcon2 register accordingly. 8. slave sets the ckp bit releasing scl. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets sspif after the ack if the r/w bit is set. 11. slave software clears sspif. 12. slave loads value to transmit to the master into sspbuf setting the bf bit. 13. slave sets ckp bit releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the 9 th scl pulse. 15. slave hardware copies the ack value into the ackstat bit of the sspcon2 register. 16. steps 10?15 are repeated for each byte transmitted to the master from the slave. 17. if the master sends a not ack the slave releases the bus allowing the master to send a stop and end the communication. note: sspbuf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the scl line to receive a stop. mcp19111 ds22331a-page 160 ? 2013 microchip technology inc. figure 27-11: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ackdt ackstat ckp r/w d/a received address is read from sspbuf bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspbuf cleared by software slave clears ackdt to ack address master?s ack response is copied to sspstat ckp not cleared after not ack set by software, releases scl acktim is cleared on 9th rising edge of scl acktim is set on 8th falling edge of scl when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sdax to slave for ack sequence ack ack acktim ? 2013 microchip technology inc. ds22331a-page 161 mcp19111 27.4.5 slave mode 10-bit address reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 10-bit addressing mode. figure 27-12 is used as a visual reference for this description. this is a step-by-step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of sspstat is set; sspif is set, if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the sspstat register is set. 4. slave sends ack and sspif is set. 5. software clears the sspif bit. 6. software reads received address from sspbuf clearing the bf flag. 7. slave loads low address into sspaddx, releasing scl. 8. master sends matching low-address byte to the slave; ua bit is set. 9. slave sends ack and sspif is set. 10. slave clears sspif. 11. slave reads the received matching address from sspbuf clearing bf. 12. slave loads high address into sspadd. 13. master clocks a data byte to the slave and clocks out the slaves ack on the 9th scl pulse; sspif is set. 14. if sen bit of sspcon2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears sspif. 16. slave reads the received byte from sspbuf clearing bf. 17. if sen is set, the slave sets ckp to release the scl. 18. steps 13?17 repeat for each received byte. 19. master sends stop to end the transmission. 27.4.6 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the sspaddx register using the ua bit. all functionality, specifically when the ckp bit is cleared and scl line is held low, are the same. figure 27-13 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 27-14 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the sspaddx register are not allowed until after the ack sequence. note: if the low address does not match, sspif and ua are still set so that the slave soft- ware can set sspaddx back to the high address. bf is not set because there is no match. ckp is unaffected. mcp19111 ds22331a-page 162 ? 2013 microchip technology inc. figure 27-12: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sspif receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ua ckp 1 2345678 912345678 9 12345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates sspadd data is read scl is held low set by software, while ckp = 0 from sspbuf releasing scl when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from sspbuf and releases scl when ua = 1 ; if address matches set by hardware on 9th fa lling edge sspadd it is loaded into sspbuf scl is held low s bf ? 2013 microchip technology inc. ds22331a-page 163 mcp19111 figure 27-13: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sda scl sspif bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 sspbuf is read from received data sspbuf can be read anytime before the next received byte cleared by software falling edge of scl not allowed until 9th update to sspadd is set ckp with software releases scl scl clears ua and releases update of sspadd, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl cleared by software r/w = 0 mcp19111 ds22331a-page 164 ? 2013 microchip technology inc. figure 27-14: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 234 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after sspadd is updated, ua is cleared and scl is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates sspadd sspbuf loaded with received address must be updated has been received loaded into sspbuf releases scl masters not ack is copied matching address byte ckp is cleared on 9th falling edge of sclx read from sspbuf back into sspadd ackstat set by hardware ? 2013 microchip technology inc. ds22331a-page 165 mcp19111 27.4.7 clock stretching clock stretching occurs when a device on the bus holds the scl line low, effectively pausing communication. the slave may stretch the clock to allow more time to handle data or prepare a response for the master device. a master device is not concerned with stretching, as anytime it is active on the bus and not transferring data it is stretching. any stretching done by a slave is invisible to the master software and handled by the hardware that generates scl. the ckp bit of the sspcon1 register is used to control stretching in software. any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. setting ckp will release scl and allow more communication. 27.4.7.1 normal clock stretching following an ack, if the r/w bit of the sspstat is set, causing a read request, the slave hardware will clear ckp. this allows the slave time to update sspbuf with data to transfer to the master. if the sen bit of sspcon2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready; ckp is set by software and communication resumes. 27.4.7.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set, the clock is always stretched. this is the only time the scl is stretched without ckp being cleared. scl is released immediately after a write to sspaddx. 27.4.7.3 byte nacking when ahen bit of sspcon3 is set; ckp is cleared by the hardware after the 8 th falling edge of scl for a received matching address byte. when dhen bit of sspcon3 is set; ckp is cleared after the 8 th falling edge of scl for received data. stretching after the 8 th falling edge of scl allows the slave to look at the received address or data and decide if it wants to ack the received data. 27.4.8 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. therefore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 27-15 ). figure 27-15: clock synchronization timing note 1: the bf bit has no effect on if the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock or clear ckp, if sspbuf was read before the 9 th falling edge of scl. 2: previous versions of the module did not stretch the clock for a transmission if sspbuf was loaded before the 9 th falling edge of scl. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sda scl dx ? ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon1 ckp master device releases clock master device asserts clock mcp19111 ds22331a-page 166 ? 2013 microchip technology inc. 27.4.9 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master device. the exception is the general call address, which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the sspcon2 register is set, the slave module will automatically ack the reception of this address, regardless of the value stored in sspaddx. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave software can read sspbuf and respond. figure 27-16 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in the 7-bit mode. if the ahen bit of the sspcon3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8 th falling edge of scl. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 27-16: slave mode general call address sequence 27.4.10 sspmskx register an ssp mask (sspmskx) register ( register 27-6 and register 27-8 ) is available in i 2 c slave mode as a mask for the value held in the sspsrx register during an address comparison operation. a zero (? 0 ?) bit in the sspmskx register has the effect of making the corresponding bit of the received address a ?don?t care?. this register is reset to all ? 1 ?s upon any reset condition and, therefore, has no effect on standard ssp operation until written with a mask value. the ssp mask register is active during: ? 7-bit address mode: address compare of a<7:1>. ? 10-bit address mode: address compare of a<7:0> only. the ssp mask has no effect during the reception of the first (high) byte of the address. sda scl s sspif bf (sspstat<0>) cleared by software sspbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspcon2<7>) ?1? ? 2013 microchip technology inc. ds22331a-page 167 mcp19111 27.5 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspm bits in the sspcon1 register and by setting the sspen bit. in master mode, the sda and sck pins must be configured as inputs. the mssp peripheral hardware will override the output driver tris controls when necessary, to drive the pins low. master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sda and scl lines. the following events will cause the ssp interrupt flag bit, sspif, to be set (ssp interrupt, if enabled): ? start condition detected ? stop condition detected ? data transfer byte transmitted/received ? acknowledge transmitted/received ? repeated start generated 27.5.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted 8 bits at a time. after each byte is transmit- ted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received 8 bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and the end of transmission. a baud rate generator is used to set the clock frequency output on scl. see section 27.6 ?baud rate generator? for more detail. 27.5.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<7:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 27-17 ). note 1: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur. 2: when in master mode, start/stop detection is masked and an interrupt is generated when the sen/pen bit is cleared and the generation is complete. mcp19111 ds22331a-page 168 ? 2013 microchip technology inc. figure 27-17: baud rate generator timing with clock arbitration 27.5.3 wcol status flag if the user writes the sspbuf when a start, restart, stop, receive or transmit sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set, it indicates that an action on sspbuf was attempted while the module was not idle. 27.5.4 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen bit of the sspcon2 register. if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<7:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit of the sspstat1 register to be set. following this, the baud rate generator is reloaded with the contents of sspadd<7:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit of the sspcon2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. figure 27-18: first start bit timing sda scl scl deasserted but slave holds dx ? ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles note: because queueing of events is not allowed, writing to the lower 5 bits of sspcon2 is disabled until the start condition is complete. note 1: if at the beginning of the start condition, the sda and scl pins are already sam- pled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c specification states that a bus collision cannot occur on a start. sda scl s t brg 1 st bit 2 nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit ? 2013 microchip technology inc. ds22331a-page 169 mcp19111 27.5.5 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit of the sspcon2 register is programmed high and the master state machine is no longer active. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by the assertion of the sda pin (sda = 0 ) for one t brg while scl is high. scl is asserted low. following this, the rsen bit of the sspcon2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit of the sspstat register will be set. the sspif bit will not be set until the baud rate generator has timed out. figure 27-19: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ?sda is sampled low when scl goes from low-to-high. ?scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. sda scl repeated start write to sspcon2 write to sspbuf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here t brg t brg t brg and sets sspif sr mcp19111 ds22331a-page 170 ? 2013 microchip technology inc. 27.5.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf and will allow the baud rate generator to begin counting and start the next transmission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high. when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the 8 th bit is shifted out (the falling edge of the 8 th clock), the bf flag is cleared and the master releases the sda. this allows the slave device being addressed to respond with an ack bit during the 9 th bit time if an address match occurred, or if data was received properly. the status of ack is written into the ackstat bit on the rising edge of the 9 th clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the 9 th clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged ( figure 27-20 ). after the write to the sspbuf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the 8 th clock, the master will release the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the 9 th clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the sspcon2 register. following the falling edge of the 9 th clock transmission of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. 27.5.6.1 bf status flag in transmit mode, the bf bit of the sspstat register is set when the cpu writes to sspbuf, and is cleared when all 8 bits are shifted out. 27.5.6.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 27.5.6.3 ackstat status flag in transmit mode, the ackstat bit of the sspcon2 register is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 27.5.6.4 typical transmit sequence 1. the user generates a start condition by setting the sen bit of the sspcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. the mssp module will wait the required start time before any other operation takes place. 5. the user loads the sspbuf with the slave address to transmit. 6. address is shifted out the sda pin until all 8 bits are transmitted. transmission begins as soon as sspbuf is written to. 7. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 8. the mssp module generates an interrupt at the end of the 9 th clock cycle by setting the sspif bit. 9. the user loads the sspbuf with eight bits of data. 10. data is shifted out the sda pin until all 8 bits are transmitted. 11. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 12. steps 8?11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the sspcon2 register. interrupt is generated once the stop/restart condition is complete. ? 2013 microchip technology inc. ds22331a-page 171 mcp19111 figure 27-20: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine sspbuf is written by software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared by software sspbuf written pen r/w cleared by software mcp19111 ds22331a-page 172 ? 2013 microchip technology inc. 27.5.7 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen bit of the sspcon2 register. the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to- low/low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate gener- ator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable, acken bit of the sspcon2 register. 27.5.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 27.5.7.2 sspov status flag in receive operation, the sspov bit is set when 8 bits are received into the sspsr and the bf flag bit is already set from a previous reception. 27.5.7.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 27.5.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the sspcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. the user writes sspbuf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sda pin until all 8 bits are transmitted. transmission begins as soon as sspbuf is written to. 6. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 7. the mssp module generates an interrupt at the end of the 9 th clock cycle by setting the sspif bit. 8. user sets the rcen bit of the sspcon2 register and the master clocks in a byte from the slave. 9. after the 8 th falling edge of scl, sspif and bf are set. 10. master clears sspif and reads the received byte from sspuf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the sspcon2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and sspif is set. 13. the user clears sspif. 14. steps 8?13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the mssp module must be in an idle state before the rcen bit is set, or the rcen bit will be disregarded. ? 2013 microchip technology inc. ds22331a-page 173 mcp19111 figure 27-21: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 sspov sda = 0 , sclx = 1 while cpu (sspstat<0>) ack cleared by software cleared by software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspxif acken begin start condition cleared by software sda = ackdt = 0 last bit is shifted into sspsr and contents are unloaded into sspbuf rcen master configured as a receiver by programming sspcon2<3> (rcen = 1 ) rcen cleared automatically ack from master sda = ackdt = 0 rcen cleared automatically mcp19111 ds22331a-page 174 ? 2013 microchip technology inc. 27.5.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken bit of the sspcon2 register. when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to gen- erate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode ( figure 27-22 ). 27.5.8.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write does not occur). 27.5.9 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen bit of the sspcon2 register. at the end of a receive/transmit, the scl line is held low after the falling edge of the 9 th clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit of the sspstat register is set. a t brg later, the pen bit is cleared and the sspif bit is set ( figure 27-23 ). 27.5.9.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 27-22: acknowledge sequen ce waveform figure 27-23: stop cond ition receive or transmit mode sda scl sspif set at acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software sspif set at the end of acknowledge sequence cleared in software ack note: t brg = one baud rate generator period. scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set note: t brg = one baud rate generator period. ? 2013 microchip technology inc. ds22331a-page 175 mcp19111 27.5.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data, and when an address match or complete byte transfer occurs, wakes the processor from sleep (if the mssp interrupt is enabled). 27.5.11 effects of a reset a reset disables the mssp module and terminates the current transfer. 27.5.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the msspx module is disabled. control of the i 2 c bus may be taken when the p bit of the sspstat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 27.5.13 multi-master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitration. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin is ? 0 ?, then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state ( figure 27-24 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. figure 27-24: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0 mcp19111 ds22331a-page 176 ? 2013 microchip technology inc. 27.5.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 27-25 ). b) scl is sampled low before sda is asserted low ( figure 27-26 ). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted ? the bclif flag is set ? the mssp module is reset to its idle state ( figure 27-25 ). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded and counts down. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 27-27 ). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the scl pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 27-25: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared by software sspif and bclif are cleared by software set bclif, start condition. set bclif. ? 2013 microchip technology inc. ds22331a-page 177 mcp19111 figure 27-26: bus collision d uring start condition (scl = 0 ) figure 27-27: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared by software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared by software set sspif sdax = 0 , scl = 1 , sclx pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sdax. set sen, enable start sequence if sda = 1 , scl = 1 mcp19111 ds22331a-page 178 ? 2013 microchip technology inc. 27.5.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user releases sda and the pin is allowed to float high, the brg is loaded with sspadd and counts down to zero. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 27-28 ). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition (see figure 27-29 .) if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 27-28: bus collision during a repeat ed start condition (case 1) figure 27-29: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared by software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared by software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ? ? 2013 microchip technology inc. ds22331a-page 179 mcp19111 27.5.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd and counts down to 0. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? ( figure 27-30 ). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? ( figure 27-31 ). figure 27-30: bus collision during a stop condition (case 1) figure 27-31: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ? mcp19111 ds22331a-page 180 ? 2013 microchip technology inc. table 27-1: summary of registers associated with i 2 c operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page: intcon gie peie t0ie inte ioce t0if intf iocf 93 pie1 ? adie bclie sspie ? ? tmr2ie tmr1ie 94 pir1 ? adif bclif sspif ? ? tmr2if tmr1if 96 TRISGPA trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 112 trisgpb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 115 sspadd add7 add6 add5 add4 add3 add2 add1 add0 186 sspbuf synchronous serial port receive buffer/transmit register 146* sspcon1 wcol sspov sspen ckp sspm3 sspm2 sspm1 sspm0 183 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 184 sspcon3 acktim pcie scie boen sdaht sbcde ahen dhen 185 sspmsk msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 186 sspstat smp cke d/a psr/w ua bf 182 sspmsk2 msk27 msk26 msk25 msk24 msk23 msk22 msk21 msk20 187 sspadd2 add27 add26 add25 add24 add23 add22 add21 add20 187 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the mssp module in i 2 c mode. * page provides register information. ? 2013 microchip technology inc. ds22331a-page 181 mcp19111 27.6 baud rate generator the mssp module has a baud rate generator available for clock generation in i 2 c master mode. the baud rate generator (brg) reload value is placed in the sspadd register ( register 27-7 ). when a write occurs to sspbuf, the baud rate generator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal ?reload? in figure 27-32 triggers the value from sspadd to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the mssp is being operated in. table 27-2 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. equation 27-1: figure 27-32: baud rate genera tor block diagram f clock f osc sspadd 1 + ?? 4 ?? ---------------------------------------------- = sspm<3:0> brg down counter sspclk f osc /2 sspadd<7:0> sspm<3:0> scl reload control reload note: values of 0x00, 0x01 and 0x02 are not valid for sspadd when used as a baud rate generator for i 2 c. this is an implementation limitation. table 27-2: mssp clock rate w/brg f osc f cy brg value f clock (2 rollovers of brg) 8 mhz 2 mhz 04h 400 khz ( 1 ) 8 mhz 2 mhz 0bh 166 khz 8 mhz 2 mhz 13h 100 khz note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. mcp19111 ds22331a-page 182 ? 2013 microchip technology inc. register 27-2: sspstat: ssp status register r/w-0 r/w-0 r-0 r-0 r-0 r-0 r-0 r-0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 smp: data input sample bit 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: clock edge select bit 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (this bit is cleared when the mssp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 =read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive: 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit: 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty ? 2013 microchip technology inc. ds22331a-page 183 mcp19111 register 27-3: sspcon1: ssp control register 1 r/c/hs-0 r/c/hs-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 r/w-0 wcol sspov sspen ckp sspm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit ( 1 ) 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins ( 2 ) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in i 2 c slave mode: scl release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3-0 sspm<3:0>: synchronous serial port mode select bits 0000 = reserved 0001 = reserved 0010 = reserved 0011 = reserved 0100 = reserved 0101 = reserved 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc /(4 x (sspadd+1)) ( 3 ) 1001 = reserved 1010 = reserved 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf register. 2: when enabled, the sda and scl pins must be configured as inputs. 3: sspadd values of 0, 1 or 2 are not supported for i 2 c mode. mcp19111 ds22331a-page 184 ? 2013 microchip technology inc. register 27-4: sspcon2: ssp control register 2 r/w-0/0 r-0/0 r/w-0/0 r/s/hs-0/0 r/s/hs- 0/0 r/s/hs-0/0 r/s/hs-0/0 r/w/hs-0/0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sck release control: 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled bit (in i 2 c master mode only) in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled). ? 2013 microchip technology inc. ds22331a-page 185 mcp19111 register 27-5: sspcon3: ssp control register 3 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 acktim pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7 acktim: acknowledge time status bit (i 2 c mode only) ( 2 ) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on the 8 th falling edge of scl clock 0 = not an acknowledge sequence, cleared on the 9 th rising edge of scl clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled ( 1 ) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled ( 1 ) bit 4 boen: buffer overwrite enable bit in i 2 c master mode: this bit is ignored. in i 2 c slave mode: 1 = sspbuf is updated and ack is generated for a received address/data byte, ignoring the state of the sspov bit only if the bf bit = 0 . 0 = sspbuf is only updated when sspov is clear bit 3 sdaht: sda hold time selection bit 1 = minimum of 300 ns hold time on sda after the falling edge of scl 0 = minimum of 100 ns hold time on sda after the falling edge of scl bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if on the rising edge of scl, sda is sampled low when the module is outputting a high state, the bclif bit of the pir2 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the 8 th falling edge of scl for a matching received address byte; ckp bit of the sspcon1 register will be cleared and the scl will be held low. 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8 th falling edge of scl for a received data byte; slave hardware clears the ckp bit of the sspcon1 register and scl is held low. 0 = data holding is disabled note 1: this bit has no effect in slave modes that start and stop condition detection is explicitly listed as enabled. 2: the acktim status bit is only active when the ahen bit or dhen bit is set. mcp19111 ds22331a-page 186 ? 2013 microchip technology inc. register 27-6: sspmsk: ssp mask register 1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 msk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to sspadd ? 2013 microchip technology inc. ds22331a-page 187 mcp19111 register 27-8: sspmsk2: ssp mask register 2 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 r/w-1 msk2<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? -n = value at por ?1? = bit is set ?0? = bit is cleared x = bit is unknown bit 7-1 msk2<7:1>: mask bits 1 = the received address bit n is compared to sspadd2 mcp19111 ds22331a-page 188 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 189 mcp19111 28.0 in-circuit serial programming? (icsp?) icsp programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process, allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp programming: ? icspclk ? icspdat ? mclr ?v dd ?v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirectional i/o used for transferring the serial data and the icspclk pin is the clock input. the device is placed into a program/verify mode by holding the icspdat and icspclk pins low, while raising the mclr pin from v il to v ihh . 28.1 common programming interfaces connection to a target device is typically done through an icsp header. a commonly found connector on development tools is the rj-11 in the 6p6c (6 pin, 6 connector) configuration. see figure 28-1 . figure 28-1: icd rj-11 style connector interface another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 28-2 . figure 28-2: pickit-style connector interface 1 2 3 4 5 6 target bottom side pc board mclr v ss icspclk v dd icspdat nc pin description 1 = 1 = mclr 2=2 = v dd target 3=3 = v ss (ground) 4 = 4 = icspdat 5 = 5 = icspclk 6 = 6 = no connect 1 2 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = 1 = mclr 2=2 = v dd target 3=3 = v ss (ground) 4=4 = icspdat 5=5 = icspclk 6 = 6 = no connect pin 1 indicator mcp19111 ds22331a-page 190 ? 2013 microchip technology inc. for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices, such as resistors, diodes, or even jumpers. see figure 28-3 for more information. figure 28-3: typical conne ction for icsp programming v dd v pp v ss external device to be data clock v dd mclr v ss icspdat icspclk * * * to normal connections * isolation devices (as required) programming signals programmed v dd ? 2013 microchip technology inc. ds22331a-page 191 mcp19111 29.0 instruction set summary the mcp19111 instruction set is highly orthogonal and is comprised of three basic categories: ? byte-oriented operations ? bit-oriented operations ? literal and control operations each instruction is a 14-bit word divided into an opcode, which specifies the instruction type, and one or more operands, which further specify the operation of the instruction. the formats for each of the categories is presented in figure 29-1 , while the various opcode fields are summarized in table 29-1 . table 29-2 lists the instructions recognized by the mpasm tm assembler. for byte-oriented instructions, ?f? represents a file register designator and ?d? represents a destination designator. the file register designator specifies which file register is to be used by the instruction. the destination designator specifies where the result of the operation is to be placed. if ?d? is zero, the result is placed in the w register. if ?d? is one, the result is placed in the file register specified in the instruction. for bit-oriented instructions, ?b? represents a bit field designator, which selects the bit affected by the operation, while ?f? represents the address of the file in which the bit is located. for literal and control operations, ?k? represents an 8-bit or 11-bit constant, or literal value. one instruction cycle consists of four oscillator periods; for an oscillator frequency of 4 mhz, this gives a normal instruction execution time of 1 s. all instructions are executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of an instruction. when this occurs, the execution takes two instruction cycles, with the second cycle executed as a nop . all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 29.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (rmw) operation. the register is read, the data is modified, and the result is stored according to either the instruction or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. for example, a clrf porta instruction will read portgpa, clear all the data bits, then write the result back to portgpa. this example would have the unintended consequence of clearing the condition that set the iocif flag. figure 29-1: general format for instructions table 29-1: opcode field descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w, d = 1 : store result in file register f. default is d = 1. pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only mcp19111 ds22331a-page 192 ? 2013 microchip technology inc. table 29-2: mcp19111 instruction set mnemonic, operands description cycles 14-bit opcode status affecte d notes msb lsb byte-oriented file register operations addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f, d f, d f ? f, d f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110 dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c, dc, z z z z z z z z z c c c, dc, z z 1 , 2 1 , 2 2 1 , 2 1 , 2 1 , 2 , 3 1 , 2 1 , 2 , 3 1 , 2 1 , 2 1 , 2 1 , 2 1 , 2 1 , 2 1 , 2 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 01 01 01 01 00bb 01bb 10bb 11bb bfff bfff bfff bfff ffff ffff ffff ffff 1 , 2 1 , 2 3 3 literal and control operations addlw andlw call clrwdt goto iorlw movlw retfie retlw return sleep sublw xorlw k k k ? k k k ? k ? ? k k add literal and w and literal with w call subroutine clear watchdog timer go to address inclusive or literal with w move literal to w return from interrupt return with literal in w return from subroutine go into standby mode subtract w from literal exclusive or literal with w 1 1 2 1 2 1 1 2 2 2 1 1 1 11 11 10 00 10 11 11 00 11 00 00 11 11 111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010 kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk c, dc, z z to , pd z to , pd c, dc, z z note 1: when an i/o register is modified as a function of itself (e.g., movf porta, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is ? 1 ? for a pin configured as input and is driven low by an external device, the data will be written back with a ? 0 ?. 2: if this instruction is executed on the tmr0 register (and where applicable, d = 1 ), the prescaler will be cleared if assigned to the timer0 module. 3: if the program counter (pc) is modified, or a conditio nal test is true, the instruction requires two cycles. the second cycle is executed as a nop . ? 2013 microchip technology inc. ds22331a-page 193 mcp19111 29.2 instruction descriptions addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b? in register ?f? is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a two-cycle instruction. mcp19111 ds22331a-page 194 ? 2013 microchip technology inc. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a two-cycle instruction. call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<4:3>) ? pc<12:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watchdog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. ? 2013 microchip technology inc. ds22331a-page 195 mcp19111 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a two-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<4:3> ? pc<12:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incremented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a two-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. mcp19111 ds22331a-page 196 ? 2013 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register ?f? is moved to a destination dependent upon the status of ?d?. if d = 0 , destination is w register. if d = 1 , the destination is file register ?f? itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1 movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assemble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movw f option before instruction option = 0xff w = 0x4f after instruction option = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop ? 2013 microchip technology inc. ds22331a-page 197 mcp19111 retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table done call table;w contains ;table offset ;value goto done ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ;end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. mcp19111 ds22331a-page 198 ? 2013 microchip technology inc. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. register f c register f c sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. sublw subtract w from literal syntax: [ label ] sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (two?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. result condition c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> ? 2013 microchip technology inc. ds22331a-page 199 mcp19111 subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (two?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of register ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0> xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. mcp19111 ds22331a-page 200 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 201 mcp19111 30.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 30.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power. mcp19111 ds22331a-page 202 ? 2013 microchip technology inc. 30.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal controllers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 30.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 30.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 30.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 30.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility ? 2013 microchip technology inc. ds22331a-page 203 mcp19111 30.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 30.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 30.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is microchip's most cost effective high-speed hardware debugger/programmer for microchip flash digital signal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcontrollers and dspic ? dscs with the powerful, yet easy-to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 30.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and programming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. mcp19111 ds22331a-page 204 ? 2013 microchip technology inc. 30.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use interface for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcontrollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a breakpoint, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 30.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 30.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. ? 2013 microchip technology inc. ds22331a-page 205 mcp19111 31.0 packaging information 31.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead qfn (5x5x0.9 mm) example pin 1 pin 1 19111 e/mq ^^ 1246256 3 e mcp19111 ds22331a-page 206 ? 2013 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging ? 2013 microchip technology inc. ds22331a-page 207 mcp19111 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging mcp19111 ds22331a-page 208 ? 2013 microchip technology inc. 28-lead plastic quad flat, no lead package (mq) C 5x5 mm body [qfn] land pattern with 0.55 mm contact length note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging microchip technology drawing c04-2140a ? 2013 microchip technology inc. ds22331a-page 209 mcp19111 appendix a: revision history revision a (january 2013) ? original release of this document. mcp19111 ds22331a-page 210 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 211 mcp19111 index a a/d specifications.......................................................... 3, 31 a/d conversion ................................................................. 125 requirements.............................................................. 32 timing ................................................................... 32, 33 absolute maximum ratings ................................................ 21 ac characteristics .............................................................. 28 ackstat ......................................................................... 170 ackstat status flag ...................................................... 170 adc .................................................................................. 123 acquisition requirements ......................................... 129 associated registers ................................................ 131 block diagram........................................................... 123 calculating acquisition time..................................... 129 channel selection..................................................... 124 configuration............................................................. 124 configuring interrupt ................................................. 126 conversion clock...................................................... 124 conversion procedure .............................................. 126 internal sampling switch (r ss ) i mpedance .............. 129 interrupts................................................................... 125 operation .................................................................. 126 operation during sleep ............................................ 126 port configuration ..................................................... 124 register definitions................................................... 127 source impedance.................................................... 129 special event trigger................................................ 126 adcon0 register............................................................. 127 adcon1 register............................................................. 128 adresh register (adfm = 0) ......................................... 128 adresl register (adfm = 0).......................................... 128 alternate pin function....................................................... 110 analog blocks enable control ............................................ 49 analog peripheral control ................................................... 47 analog-to-digital converter. see adc ansela register ............................................................. 113 anselb register ............................................................. 116 apfcon register............................................................. 110 assembler mpasm assembler................................................... 202 b bench testing analog bench test control ......................................... 55 system ........................................................................ 55 bf ............................................................................. 170, 172 bf status flag .......................................................... 170, 172 block diagrams adc .......................................................................... 123 adc transfer function ............................................. 130 analog input model ................................................... 130 generic i/o port ........................................................ 109 interrupt logic ............................................................. 92 mclr circuit............................................................... 84 mssp (i 2 c master mode) ......................................... 145 mssp (i 2 c slave mode) ........................................... 146 on-chip reset circuit ................................................. 83 simplified pwm......................................................... 142 timer0....................................................................... 133 timer1....................................................................... 135 timer2....................................................................... 138 watchdog timer........................................................ 101 block diagrams mcp19111.................................................. 8 c c compilers mplab c18 .............................................................. 202 calibration word associated registers.................................................. 82 capture/compare/pwm ........................................... 141, 143 clock switching .................................................................. 82 code examples a/d conversion ........................................................ 126 assigning prescaler to timer0.................................. 134 assigning prescaler to wdt..................................... 134 initializing porta .................................................... 109 saving status and w registers in ram ..................... 98 compensation .................................................................... 16 compensation setting ........................................................ 41 computed function calls ................................................... 76 computed goto................................................................ 76 current measurement control ................................................. 49 current sense ........................................................ 16, 38, 39 customer change notification service............................. 217 customer support............................................................. 217 d data memory ...................................................................... 68 data memory map .............................................................. 70 dc and ac characteristics................................................. 51 graphs and tables ..................................................... 51 dc characteristics.............................................................. 28 development support ....................................................... 201 device configuration ........................................................ 35, 79 code protection.................................................. 80 configuration word............................................. 79 id locations ....................................................... 80 user id ............................................................... 80 write protection .................................................. 80 device calibration............................................................... 57 calibration word 1...................................................... 57 calibration word 2...................................................... 58 calibration word 3...................................................... 59 calibration word 4...................................................... 60 calibration word 5...................................................... 61 calibration word 6...................................................... 62 calibration word 7...................................................... 63 device overview................................................................... 7 digital electrical characteristics ......................................... 27 diode emulation mode ....................................................... 47 e eccp/ccp. see enhanced capture/compare/pwm electrical characteristics .............................................. 21, 22 errata .................................................................................... 5 external clock..................................................................... 28 mcp19111 ds22331a-page 212 ? 2013 microchip technology inc. f features microcontroller .............................................................. 1 miscellaneous ............................................................. 19 protection .................................................................... 18 synchronous buck ........................................................ 1 firmware instructions........................................................ 191 flash program memory control ........................................ 103 operation during code protect................................. 107 operation during write protect .................................. 107 protecting .................................................................. 107 reading..................................................................... 106 writing to ................................................................... 107 flash program memory control registers........................ 104 h high-side drive strength .................................................... 47 i i/o ports.......................................................................... 109 i 2 c mode (msspx) acknowledge sequence ........................................... 150 acknowledge sequence timing................................ 174 associated registers ................................................ 180 bus collision during a repeated start condition ................... 178 during a start condition.................................... 176 during a stop condition.................................... 179 effects of a reset...................................................... 175 i 2 c clock rate w/brg .............................................. 181 master mode ............................................................. 167 clock arbitration................................................ 167 operation .......................................................... 167 reception.......................................................... 172 start condition timing .............................. 168, 169 transmission..................................................... 170 multi-master communication, bus collision and arbitration.......................................................... 175 multi-master mode .................................................... 175 operation .................................................................. 148 overview ................................................................... 146 read/write bit information (r/w bit) ........................ 151 slave mode 10-bit address reception.................................. 161 bus collision ..................................................... 157 clock synchronization ...................................... 165 general call address support .......................... 166 operation .......................................................... 151 sspmskx register........................................... 166 transmission..................................................... 157 sleep operation ........................................................ 175 stop condition timing............................................... 174 in-circuit serial programming (icsp) ............................... 189 common programming interfaces ............................ 189 indirect addressing ............................................................. 76 input .................................................................................... 22 type ............................................................................ 10 under voltage lockout ......................................... 18, 35 instruction format ............................................................. 191 instruction set ................................................................... 191 addlw ..................................................................... 193 addwf ..................................................................... 193 andlw ..................................................................... 193 andwf ..................................................................... 193 movf ....................................................................... 196 bcf .......................................................................... 193 bsf........................................................................... 193 btfsc ...................................................................... 193 btfss ...................................................................... 194 call......................................................................... 194 clrf ........................................................................ 194 clrw ....................................................................... 194 clrwdt .................................................................. 194 comf ....................................................................... 194 decf ........................................................................ 194 decfsz ................................................................... 195 goto ....................................................................... 195 incf ......................................................................... 195 incfsz..................................................................... 195 iorlw ...................................................................... 195 iorwf...................................................................... 195 movlw .................................................................... 196 movwf .................................................................... 196 nop .......................................................................... 196 retfie ..................................................................... 197 retlw ..................................................................... 197 return................................................................... 197 rlf ........................................................................... 198 rrf .......................................................................... 198 sleep ...................................................................... 198 sublw ..................................................................... 198 subwf..................................................................... 199 swapf ..................................................................... 199 xorlw .................................................................... 199 xorwf .................................................................... 199 summary table ........................................................ 192 internal sampling switch (r ss ) i mpedance ...................... 129 internal synchronous driver ............................................... 15 internal temperature indicator module............................. 121 circuit operation....................................................... 121 temperature output ................................................. 121 internal temperature measurement control....................... 49 internet address ............................................................... 217 interrupt-on-change......................................................... 119 interrupt-on-change associated registers ................................................ 120 clearing interrupt flags ............................................ 119 enabling the module ................................................. 119 operation in sleep .................................................... 119 pin configuration ...................................................... 119 registers .................................................................. 120 interrupts adc .......................................................................... 126 associated registers .................................................. 97 context saving ........................................................... 98 control registers ........................................................ 93 ra2/int ...................................................................... 91 tmr1 ........................................................................ 136 l linear regulators ............................................................... 15 ? 2013 microchip technology inc. ds22331a-page 213 mcp19111 m master error signal gain ................................................ 43 master synchronous serial port. see msspx mclr .................................................................................. 84 internal ........................................................................ 84 memory organization.......................................................... 67 data ............................................................................ 68 program ...................................................................... 67 microchip internet web site .............................................. 217 mosfet ................................... 13, 14, 15, 36, 44, 47, 55, 65 driver dead time........................................................ 15 mosfet driver dead time .................................................................. 47 programmable dead time.......................................... 44 mplab asm30 assembler, linker, librarian ................... 202 mplab integrated development environment software .. 201 mplab pm3 device programmer .................................... 204 mplab real ice in-circuit emulator system................. 203 mplink object linker/mplib object librarian ................ 202 msspx .............................................................................. 145 arbitration.................................................................. 148 baud rate generator................................................ 181 clock stretching........................................................ 148 i 2 c bus terms .......................................................... 149 i 2 c master mode....................................................... 167 i 2 c mode................................................................... 146 i 2 c mode operation .................................................. 148 i 2 c slave mode operation ........................................ 151 module overview ...................................................... 145 multi-phase system ............................................................ 20 o opcode field descriptions ............................................. 191 oscillator ............................................................................. 81 associated registers .................................................. 82 calibration................................................................... 81 delay upon power-up................................................. 82 frequency tuning ....................................................... 81 internal oscillator ........................................................ 81 oscillator module ................................................................ 82 output ................................................................................. 47 multiple system........................................................... 20 overcurrent ..................................................... 18, 36, 37 overvoltage..................................................... 18, 23, 46 overvoltage enable .................................................... 49 power good ................................................................ 20 type ............................................................................ 10 under voltage ................................................. 18, 23, 46 under voltage accelerator.......................................... 47 under voltage enable................................................. 49 voltage........................................................................ 16 soft-start............................................................. 20 tracking .............................................................. 20 voltage configuration ................................................. 45 voltage sense pull-up/pull-down................................ 47 overcurrent ......................................................................... 37 overvoltage accelerator ..................................................... 47 p packaging ......................................................................... 205 marking..................................................................... 205 pcl..................................................................................... 76 modifying .................................................................... 76 pclath ............................................................................. 76 pcon register ............................................................. 85, 90 pickit pickit 2 debug express ........................................... 204 pickit 2 development programmer/debugger ......... 204 pickit 3 debug express ........................................... 203 pickit 3 in-circuit debugger/programmer................ 203 pin diagram .......................................................................... 2 pinout description summary ...................................................................... 3 pinout descriptions mcp19111.................................................................. 10 pir1 register ..................................................................... 96 pir2 register ..................................................................... 97 pmadrh register............................................................ 103 pmadrl register .................................................... 103, 104 pmcon1 register .................................................... 103, 105 pmcon2 register ............................................................ 103 pmdath register ............................................................ 104 pmdatl register............................................................. 104 pmdrh register .............................................................. 105 portb additional pin functions weak pull-up .................................................... 115 pin descriptions and diagrams ................................ 117 portgpa ................................................................ 110, 119 ansela register ..................................................... 111 associated registers................................................ 113 functions and output priorities ................................ 111 interrupt-on-change ................................................. 110 weak pull-ups.......................................................... 110 portgpa register.......................................................... 110 portgpb ................................................................ 114, 119 anselb register ..................................................... 114 associated registers................................................ 117 functions and output priorities ................................ 114 interrupt-on-change ................................................. 114 p1b/p1c/p1d.capture/compare/pwm ................... 114 weak pull-ups.......................................................... 114 portgpb register.................................................. 114, 115 power-down mode (sleep)................................................. 99 associated registers................................................ 100 power-on reset (por)....................................................... 84 power-up timer (pwrt) .................................................... 85 prescaler, timer1 select (t1ckps1:t1ckps0 bits) .............................. 44 product identification system ........................................... 219 program memory ................................................................ 67 map and stack (mcp19111) ...................................... 67 program memory protection............................................... 80 programming, device instructions.................................... 191 pulse-width modulation...................................................... 31 associated registers................................................ 143 duty cycle ................................................................ 143 module...................................................................... 141 operating during sleep............................................. 143 period ....................................................................... 142 stand-alone mode .................................................... 141 standard mode ......................................................... 141 switching frequency synchronization mode............ 141 mcp19111 ds22331a-page 214 ? 2013 microchip technology inc. r reader response ............................................................. 218 read-modify-write operations.......................................... 191 register ovfcon (output voltage set point fine control) ..... 45 registers abecon (analog block enable control).................... 50 adcon0 (adc control 0) ........................................ 127 adcon1 (adc control 1) ........................................ 128 adresh (adc result high) with adfm = 0)........... 128 adresl (adc result low) with adfm = 0) ............ 128 ansela (analog select gpa).................................. 113 anselb (analog select gpb).................................. 116 apfcon (alternate pin function control)................ 110 atstcon (analog bench test control) .................... 55 buffcon (unity gain buffer control) ....................... 56 calwd1 (calibration word 1).................................... 57 calwd2 (calibration word 2).................................... 58 calwd3 (calibration word 3).................................... 59 calwd4 (calibration word 4).................................... 60 calwd5 (calibration word 5).................................... 61 calwd6 (calibration word 6).................................... 62 calwd7 (calibration word 7).................................... 63 cmpzcon (compensation setting control) .............. 41 csdgcon (voltage for zero current control).......... 39 csgscon (current sense ac gain control) ............ 38 deadcon (driver dead time control) ...................... 44 deviceid (device id) ................................................ 80 intcon (interrupt control) ......................................... 93 ioca (interrupt-on-change portgpa) ................... 120 iocb (interrupt-on-change portgpb) ................... 120 lpcrcon (slope compensation ramp control)....... 42 occon (output overcurrent control) ....................... 37 oovcon (output overvoltage detect level control)46 option_reg (option) .............................................. 75 osctune (oscillator tuning) .................................... 81 ouvcon (output under voltage detect level control) 46 ovccon (output voltage set point coarse control) 45 pcon (power control) ........................................ 85, 90 pe1(analog peripheral enable 1 control) .................. 48 pie1 (peripheral interrupt enable) .............................. 94 pir1 (peripheral interrupt flag) .................................. 96 pir2 (peripheral interrupt flag) .................................. 97 pmadrl (program memory address)...................... 104 pmcon1 (program memory control) ....................... 105 pmdath (program memory data) ........................... 104 pmdatl (program memory data)............................ 104 pmdrh (program memory address)........................ 105 portgpa ................................................................ 111 portgpb ................................................................ 115 releff (relative efficiency measurement) .............. 65 reset values............................................................... 87 slvgncon (master error signal input gain control) 43 special registers summary...................... 71, 72, 73, 74 sspcon1(ssp control)........................................... 183 sspstat (ssp status)............................................ 182 sspxadd (msspx address and baud rate, i 2 c mode) 186, 187 sspxcon1 (msspx control 1) ................................ 183 sspxcon2 (sspx control 2) ................................... 184 sspxcon3 (sspx control 3) ................................... 185 sspxmsk (sspx mask) ................................... 186, 187 sspxstat (sspx status) ........................................ 182 status ..................................................................... 69 t1con (timer1 control) .......................................... 136 trisa (tri-state porta)......................................... 112 trisgpb ( portgpb tri-state) ............................. 115 txcon ..................................................................... 139 vinlvl (input under voltage lockout control).......... 35 vzccon (voltage for zero current control).............. 40 wpub (weak pull-up portb)................................. 112 wpugpa weak pull-up portgpa.................................. 112 wpugpb (weak pull-up portgpb) ...................... 116 relative efficiency circuity control ..................................... 49 relative efficiency measurement ....................................... 65 procedure ................................................................... 65 relative efficiency measurement control........................... 49 reset .................................................................................. 83 determining causes ................................................... 89 resets................................................................................. 83 associated registers .................................................. 90 revision history................................................................ 209 s signal chain control........................................................... 49 sleep wake-up from ............................................................. 99 wake-up using interrupts ......................................... 100 slope compensation .................................................... 16, 42 slope compensation control.............................................. 49 software simulator (mplab sim) .................................... 203 special event trigger ....................................................... 126 special function registers ................................................. 69 special registers summary bank 0 ........................................................................ 71 bank 1 ........................................................................ 72 bank 2 ........................................................................ 73 bank 3 ........................................................................ 74 sspxadd register................................................... 186, 187 sspxcon1 register ........................................................ 183 sspxcon2 register ........................................................ 184 sspxcon3 register ........................................................ 185 sspxmsk register................................................... 186, 187 sspxov............................................................................ 172 sspxov status flag ........................................................ 172 sspxstat register ......................................................... 182 r/w bit ..................................................................... 151 stack................................................................................... 76 start-up sequence.............................................................. 85 status register ............................................................... 69 switching frequency .......................................................... 16 system bench testing .................................................. 20, 55 ? 2013 microchip technology inc. ds22331a-page 215 mcp19111 t t1con register ............................................................... 136 t1ckps1:t1ckps0 bits ............................................ 44 temperature indicator module .......................................... 121 thermal specifications........................................................ 26 timer requirements reset, watchdog timer, oscillator start-up timer and power-up ............................................................ 30 timer0 ....................................................................... 133, 139 8-bit counter mode................................................... 133 8-bit timer mode....................................................... 133 associated registers ................................................ 134 external clock........................................................... 134 operation .................................................................. 133 operation during sleep ............................................ 134 t0cki........................................................................ 134 timer0 module .................................................................. 133 timer1 ............................................................................... 135 associated registers ................................................ 137 associated registers.................................................. 137 clock source selection............................................. 135 control register ........................................................ 136 interrupt..................................................................... 136 operation .................................................................. 135 operation during sleep ............................................ 136 prescaler................................................................... 136 sleep......................................................................... 136 tmr1h register ....................................................... 135 tmr1l register........................................................ 135 timer1 module .................................................................. 135 timer2 associated registers.................................................. 139 control register ........................................................ 139 operation .................................................................. 138 timer2 module .................................................................. 138 timer2/4/6 associated registers ................................................ 139 timers timer1 t1con.............................................................. 136 timer2/4/6 txcon ............................................................. 139 timing diagrams acknowledge sequence ........................................... 174 baud rate generator with clock arbitration ............. 168 brg reset due to sda arbitration during start condition........................................................... 177 bus collision during a repeated start condition (case 1) ............................................................ 178 bus collision during a repeated start condition (case 2) ............................................................ 178 bus collision during a start condition (scl = 0) ..... 177 bus collision during a stop condition (case 1) ....... 179 bus collision during a stop condition (case 2) ....... 179 bus collision during start condition (sda only) ...... 176 bus collision for transmit and acknowledge............ 175 capture/compare/pwm.............................................. 31 clock synchronization .............................................. 165 first start bit timing ................................................. 168 i 2 c master mode (7 or 10-bit transmission) ............ 171 i 2 c master mode (7-bit reception)........................... 173 i 2 c stop condition receive or transmit mode ......... 174 int pin interrupt.......................................................... 92 power-up timer .......................................................... 29 repeat start condition.............................................. 169 reset .......................................................................... 29 start-up timer............................................................. 29 time-out sequence case 1 ................................................................ 85 case 2 ................................................................ 86 case 3 ................................................................ 86 timer0 ........................................................................ 30 timer1 ........................................................................ 30 wake-up from interrupt............................................. 100 watchdog timer ......................................................... 29 timing parameter symbology ............................................ 27 timing requirements clkout and i/o ........................................................ 29 external clock ............................................................ 28 trisa register................................................................. 112 TRISGPA .......................................................................... 110 TRISGPA register............................................................ 110 trisgpb register.................................................... 114, 115 txcon (timer2/4/6) register .......................................... 139 typical application circuit..................................................... 7 typical performance curves .............................................. 51 u under voltage lockout input............................................................................ 35 unity gain buffer ................................................................ 56 v voltage for zero current.................................................... 40 w watchdog timer (wdt).............................................. 85, 101 associated registers................................................ 102 configuration word w/ watchdog timer................... 102 operation.................................................................. 101 period ....................................................................... 101 programming considerations ................................... 101 wcol ....................................................... 168, 170, 172, 174 wcol status flag.................................... 168, 170, 172, 174 wpub register................................................................. 112 wpugpb register ........................................................... 116 www address ................................................................. 217 www, on-line support ..................... .................................. 5 mcp19111 ds22331a-page 216 ? 2013 microchip technology inc. notes: ? 2013 microchip technology inc. ds22331a-page 217 mcp19111 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?cus- tomer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support mcp19111 ds22331a-page 218 ? 2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds22331a mcp19111 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? ? 2013 microchip technology inc. ds22331a-page 219 mcp19111 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx package temperature range device device: mcp19111: digitally enhanced power analog controller with integrated synchronous driver tape and reel option: blank = standard packaging (tube) t = tape and reel temperature range: e= -40 ? c to +125 ? c (extended) package: mq = 28-lead plastic quad flat, no lead package - 5x5x0.9 mm body (qfn) examples: a) mcp19111-e/mq: extended temperature, qfn 5x5 package a) mcp19111t-e/mq: tape and reel, extended temperature, qfn 5x5 package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. [x] (1) tape and reel option - mcp19111 ds22331a-page 220 ? 2013 microchip technology inc. notice to customers this product is subject to a license from power-one ? , inc. related to digital power technology (dpt) patents owned by power-one, inc. this license does not extend to stand-alone power supply products. ? 2013 microchip technology inc. ds22331a-page 221 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, app lication maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. & kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 978-1-62076-959-1 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == ds22331a-page 222 ? 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